Trends in ESD Protection Design for I/O Libraries in Advanced CMOS and FINFET Technologies

Volume 6 Issue 3 June - August 2018

Research Paper

Trends in ESD Protection Design for I/O Libraries in Advanced CMOS and FINFET Technologies

Oleg Semenov * , Lyubov Leskova**, Svetlana Gerasimova ***, Dmitry Vasiounin****

* Project Leader, NXP Semiconductors, Moscow, Russia.

**,*** Layout designer, NXP Semiconductors, Moscow, Russia.

**** Circuit Design Engineer, NXP Semiconductors, Moscow, Russia.

Semenov, O., Leskova, L., Gerasimova, S., and Vasiounin, D. (2018). Trends in ESD Protection Design For I/O Libraries in Advanced CMOS and Finfet Technologies. i-manager’s Journal on Circuits and Systems, 6(3), 1-8. https://doi.org/10.26634/jcir.6.3.14878

Abstract

This paper discusses the trends in ESD protection design used in I/O libraries in advanced CMOS and FinFet technologies. The trends and guidelines are provided predominantly for low voltage I/O libraries that are commonly used for general purpose interfaces and industrial low voltage interfaces such as, GPIO, DDR, LVDS, etc. Additionally, the impact of technology scaling on ESD qualification targets for CDM stress is considered.