Pilot Protection Principle Unaffected by Influence of Capacitive Current of EHV/UHV Lines

Vol. 4  Issue 3
Year: 2016
Issue:Jun-Aug
Title:Pilot Protection Principle Unaffected by Influence of Capacitive Current of EHV/UHV Lines
Author Name:Piyush S. Rane, Rahul D. Jawale and Prashant D. Debre
Synopsis:

A pilot protection principle for transmission lines based on fault component integrated impedance, defined as the fraction of the sum of the fault component voltage phasors across the two terminals of the transmission line to the sum of the current phasors through the same line is proposed in this paper. The magnitude of the fault component integrated impedance becomes large and reflects the capacitive impedance of the line when an external fault occurs on the line, whereas in case of internal fault on the transmission line, the magnitude of the fault component integrated impedance
becomes relatively small which reflects the impedance of the system and the line. Therefore, this characteristic distinguishes the external fault and the internal fault on the transmission line. The capacitive current of the transmission line has no effect on the criterion proposed in this paper. Extensive simulation studies are carried out to verify the high sensitivity and reliability of the proposed principle by using the power system simulation software PSCAD under internal and external line to ground (L-G) fault conditions.

Modeling and Simulation of Field Oriented Controlled (FOC) Technique on a VSI for PMSM Drive

Vol. 4  Issue 3
Year: 2016
Issue:Jun-Aug
Title:Modeling and Simulation of Field Oriented Controlled (FOC) Technique on a VSI for PMSM Drive
Author Name:Vikas Patel and Vivek Patel
Synopsis:

This paper contains the modelling and simulation result of classical (vector control) field oriented control and Space Vector Pulse Width Modulation (SVPWM) voltage source inverter fed Permanent Magnet Synchronous Motor (PMSM). Permanent magnet motor drives are used in many industrial applications such as driving the robot and CNC machine tool. The precise control of a permanent magnet motor drive is not easy due to the presence of nonlinearities in Permanent magnet motor servo systems, parameter and load torque variations. Advanced pulse width modulation and
control techniques, such as Space Vector Pulse Width Modulation and Field Oriented Control, have been used for the closed-loop control of the system. Next, a model of diode-rectified two-level voltage source inverter is developed for simulations. A comparative study of indirect space vector modulated direct two-level voltage source inverter converter and space vector modulated diode-rectified two-level voltage source inverter is given interms of input/output waveforms to verify that the converter fulfills the two-level voltage source inverter operation.

Comparative Study of Modelling Techniques for Transformerless Three Phase NPC Inverter to Eliminate Harmonic in PV System

Vol. 4  Issue 3
Year: 2016
Issue:Jun-Aug
Title:Comparative Study of Modelling Techniques for Transformerless Three Phase NPC Inverter to Eliminate Harmonic in PV System
Author Name:Romi Choudhary and A.N. Tiwari
Synopsis:

The main objective of this paper is the proposal of new modulation techniques for three phase transformerless neutral point clamped inverters to eliminate harmonics in photovoltaic systems without requiring any modification on the multilevel inverter or any additional hardware. The modulation techniques are capable of reducing the harmonics in photovoltaic systems by applying PWM (Pulse Width Modulation) and SVPWM (Space Vector Pulse Width Modulation) or
converter. A multilevel power conversion concept is based on the combination of Neutral-Point -Clamped (NPC) and floating capacitor converters. In the proposed scheme, the voltage balancing across the floating capacitors is achieved by using a proper selection of redundant switching states, the input source is PV System. The output voltage waveforms in neutral point clamped inverters can be generated at low switching frequency losses with high efficiency and low distortions. This paper presents the switching pattern to generate symmetrical gating signal to control NPCVSI (Neutral Point Clamp Voltage Source Inverter) using matlab/simulink.

An Efficient Hybrid PFSCL based Implementation of Asynchronous Pipeline

Vol. 4  Issue 3
Year: 2016
Issue:Jun-Aug
Title:An Efficient Hybrid PFSCL based Implementation of Asynchronous Pipeline
Author Name:Naman Saxena, Shruti Dutta and Neeta Pandey 
Synopsis:

In this paper, Positive Feedback Source Coupled Logic (PFSCL) based asynchronous pipeline implementation is addressed. Existing Conventional PFSCL and a more efficient Triple-Tail Cell-based PFSCL variant are used for this purpose. Striking a trade-off between both topologies, a new hybrid implementation of the pipeline has been proposed. The concept is elucidated through FIFO sequencer. The hybrid implementation of asynchronous pipeline results in lesser number of gates as well as lower average power dissipation, thus not only making the circuit more efficient but also reducing overall
area overhead. The validity of the proposal is confirmed through SPICE simulations using 0.18 um CMOS technology parameters.

Fuzzy Modelling of Tunnel Diode Circuit

Vol. 4  Issue 3
Year: 2016
Issue:Jun-Aug
Title:Fuzzy Modelling of Tunnel Diode Circuit
Author Name:Mohd Aqib and Santosh Kumar Suman 
Synopsis:

This paper presents the T-S fuzzy model of the tunnel diode circuit which is one of the well-known benchmark in non-linear problem. The non-linear differential equation of tunnel diode is linearized with the help of T-S fuzzy model which consists of a number of linear sub-systems. At the end, it was observed that the over-all fuzzy system is unstable, so the fuzzy controller using Parallel Distributed Compensation (PDC) approach is employed for its stable working.

OFCC Based Shadow Filter

Vol. 4  Issue 2
Year: 2016
Issue:Mar-May
Title:OFCC Based Shadow Filter
Author Name:Prashant Gola, Prateek Tripathi, Prateek Pahalwan, Neeta Pandey and Rajeshwari Pandey
Synopsis:

This paper proposes an Operational Floating Current Conveyor (OFCC) based shadow filter configuration. The operation of the filter is based on modifying filter performance parameters with the help of gain of active block. This flexibility makes it attractive in comparison to a design, where similar control is achieved by changing values of relatively larger number of components. The proposed filter uses four active blocks (OFCCs), two grounded capacitors, and four grounded resistors and helps achieve low pass controlled low pass, high pass and band pass response. The use of grounded passive components makes proposed configuration, attractive from integrated circuit realization viewpoint. The functionality of the proposed circuit is demonstrated through SPICE simulations using the 0.5 m CMOS process model of MOSIS (AGILENT). The proposed circuit can be readily used in today's multi-standard transceivers in the IF stage for the implementation of frequency agile filters, which offer higher configurability to the transceiver chain and the analog front-end towards various standards of the ever changing industry demands.

Multimode OTRA Based Semi-Gaussian Shaper.

Vol. 4  Issue 2
Year: 2016
Issue:Mar-May
Title:Multimode OTRA Based Semi-Gaussian Shaper.
Author Name:Varun Kumar Ahalawat, V. Venkatesh Kumar, Chetna Malhotra, Neeta Pandey and Rajeshwari Pandey 
Synopsis:

Operational Transresistance Amplifier (OTRA) is a Current Controlled Voltage Source (CCVS) characterized by low impedance, thereby producing circuits insensitive to stray capacitances. This paper presents an OTRA implementation of a multimode semi Gaussian (S-G) shaper that supports voltage and transimpedance modes of operation. A comparative study of performance indicators like Signal to Noise Ratio (SNR) and Total Harmonic Distortion (THD) is included. The results obtained from SPICE simulations using 0.5 μm CMOS technology model parameters depict a perfect Gaussian shaped output waveform that contributes towards decreasing Inter Symbol Interference (ISI) by overcoming irregularities during transmission of pulse in the channel.

Analysis of Carbon Nanotube Field-Effect Transistor

Vol. 4  Issue 2
Year: 2016
Issue:Mar-May
Title:Analysis of Carbon Nanotube Field-Effect Transistor
Author Name:Bal Krishan, Sanjai Kumar Agarwal and Sanjeev Kumar 
Synopsis:

This paper explores the insights of the most outstanding application of carbon nanotube in electronic field, the carbon nanotube field-effect transistor (CNFET). The motivation of research in CNFET is fuelled by the unique electrical features of CNT, especially the semiconducting feature. Besides, the continuous effort to find future nanoelectronic device that can perform as excellent as MOSFET also push the research of CNFET to be more aggressive. The first section gives an overview of the structure of CNFET followed by the explanation of CNFET operation as a switching device. The next section provides the comparison between CNFET and MOSFET. In this paper, a comparison is being made between conventional MOSFET and different types of CNFETs, and finally concluded a future replacement of MOSFET. The major difference in CNFETs and MOSFET is that it has CNT in channel instead of Silicon. CNFETs show improved characteristics with scaling of technology. CNFET bandgap is directly affected by its chirality and diameter, which is the biggest advantage over MOSFETs. The study of various types of CNFETs comparison has been made in this paper.

An Optimized Low Power Self-Resetting Logic Design Approach

Vol. 4  Issue 2
Year: 2016
Issue:Mar-May
Title:An Optimized Low Power Self-Resetting Logic Design Approach
Author Name:Shivani Kulshrestha and Vikas Kumar Rai
Synopsis:

This paper presents a new optimized technique to power reduction and performance improvement based on selfresetting logic. The concept of self-resetting logic uses the concept of resetting the output logic automatically after a certain time span. The proposed circuit eliminates the problems of SRLGDI logic proposed previously. SRLGDI was proven to be better than dynamic logic, CMOS self-resetting logic and GDI. Three designs of full adders were made using SRLGDI and a final proposed design was made using modified SRLGDI logic and compared to three SRLGDI designs to prove the performance improvement achieved using the modified SRLGDI logic.

Distribution Systems Reliability Analysis with Power Quality issues and Neutral Currents Compensation Mistreatment MLI-DSTATCOM

Vol. 4  Issue 2
Year: 2016
Issue:Mar-May
Title:Distribution Systems Reliability Analysis with Power Quality issues and Neutral Currents Compensation Mistreatment MLI-DSTATCOM
Author Name:T. Rakesh, V. Madhusudhan and M. Sushama
Synopsis:

The “Multilevel Converter” has a massive interest at intervals for the vigour programs enterprise. The fundamental constitution of the construction converter is to decompose a curving voltage from some stages of voltages. Construction voltage offer converters area unit manufacturing as a latest breed of energy converter choice for prime energy applications. These converter topologies will generate high-quality voltage waveforms with vigor semiconductor switches acting at a frequency shut. Among the three construction converter topologies, the five-level and 7-level construction convertors constitute a promising replacement, providing a standard style that will be extended to permit an electrical device-less affiliation. This paper offers a three-segment, five stages and 7 stages cascaded construction voltage supply electrical converter headquartered DSTATCOM for vigour line learning to create stronger vigour satisfactory at intervals of the distribution network. Eventually, a curving PWM (SPWM) procedure is adopted to look at the potency of MLI based DSTATCOM. The outcomes the area unit brought by suggests that of Mat science lab / Simulink application package deal.

OTRA Based Phase Detector Design

Vol. 4  Issue 1
Year: 2016
Issue:Dec-Feb
Title:OTRA Based Phase Detector Design
Author Name:Malisetty Mamatha and C. V. Sudhakar
Synopsis:

Operational Transresistance Amplifier (OTRA) is an inherently suitable active building block for analog VLSI applications, since the OTRA is not slew limited in the same fashion as voltage op amps [2]. It can provide a high bandwidth independent of the gain. Hence, it does not suffer from constant gain bandwidth product like voltage op amps circuits [8]. An Operational Transresistance Amplifier (OTRA) based phase detector circuit has been proposed, due to the fact that both input and output terminals of OTRA are characterized by low impedance. The proposed circuit is simple to realize and consists of two OTRA based comparators, a CMOS XOR circuit, buffer and an RC integrator.

Power Gating Techniques for Leakage Reduction in CMOS Circuits - A Brief Survey.

Vol. 4  Issue 1
Year: 2016
Issue:Dec-Feb
Title:Power Gating Techniques for Leakage Reduction in CMOS Circuits - A Brief Survey.
Author Name:M. Kavitha and T. Govindaraj
Synopsis:

In this modern era, the challenge for IC designers is to maintain a prolonged battery lifetime in portable devices as power consumption is soaring with increased functionality and operating frequency. Excessive power consumption is the major barrier to the advancement of nanoscale CMOS VLSI circuits. Leakage currents are important sources of power consumption in sub-nanometre regime designs. The main sources of leakage are sub threshold leakage, gate leakage, gate induced drain leakage and junction leakage. Sub threshold leakage is the major contributor of static power and minimizing this component is more important in order to alleviate static power. The portable electronic gadgets like smartphones, tablet computers, etc., generally has much longer stand-by period than the operating period. Therefore an increased stand-by current wastes battery power seriously due to leakage. Power gating techniques help to minimize the leakage currents and increase the performance of integrated circuits. The basic strategy of power gating is to provide two power modes, a sleep mode and an active mode. The goal is to switch between these modes at the appropriate time and in the appropriate manner to maximize power savings while decreasing the impact to performance. This paper gives an overview of power gating techniques for controlling static power dissipation and retaining data in stand by periods.

Efficient Realization of Reversible Gray to Binary Code Converter Circuit

Vol. 4  Issue 1
Year: 2016
Issue:Dec-Feb
Title:Efficient Realization of Reversible Gray to Binary Code Converter Circuit
Author Name:Gowthami P.
Synopsis:

In present years, reversible logic has attained importance in many applications in the field of Quantum Computing, Nanotechnology, Low Power CMOS Design, Cryptography, etc. Without reversible logic, it is not possible to realize quantum computing. Code converters are combinational circuits which are used in digital systems designed to enhance the security of data and to decrease the hardware complexity. This paper presents a design for the reversible gray to binary code converter circuit. The main aim in the reversible logic design is to minimize the number of reversible gates used and the garbage output produced. The proposed design is compared to the existing designs in terms of parameters such as reversible gates, constant inputs, garbage outputs, and quantum cost.

Design of Wideband Sub-Harmonic Receiver Front-End Using 0.18µm CMOS Technology

Vol. 4  Issue 1
Year: 2016
Issue:Dec-Feb
Title:Design of Wideband Sub-Harmonic Receiver Front-End Using 0.18µm CMOS Technology
Author Name:K. Rajesh and K. Neelima
Synopsis:

In modern CMOS technology, the growing demand of low cost integrated circuit requires RFICs featuring low power consumption, high level integration and high data rates, have become critical in wireless systems at around 10 GHz for emerging applications. By employing silicon-based technology it is possible to design low cost direct conversion receivers targeted at 8 - 40 GHz frequency bands. The main focus is on the design and implementation of a receiver front-end for Ka - band (27 - 40 GHz) applications. The drawbacks of these designs are LO self-mixing and 1/f noise. To overcome these drawbacks, a dual - band receiver is proposed to be designed by adopting a wideband two stage LNA and wideband mixer in a 0.18 μm Bipolar Technology. To suppress the LO self-mixing problems, the sub harmonic mixer is applied to the receiver and by adopting a 3D inductor, IF 3-dB bandwidth can be improved. The designs are modeled in SPICE and verified in HSPICE Synopsys tools.

Multricor [“Multiple Trichotomous Correlation”Analysis]: The Post Hoc Examination and Measurement of Statistically Significant Tri–Squared Tests to Determine the Total and Internal Strength of Relationships between Trichotomous Variables Used For Dynamic Psychometric Circuit Assessment.

Vol. 4  Issue 1
Year: 2016
Issue:Dec-Feb
Title:Multricor [“Multiple Trichotomous Correlation”Analysis]: The Post Hoc Examination and Measurement of Statistically Significant Tri–Squared Tests to Determine the Total and Internal Strength of Relationships between Trichotomous Variables Used For Dynamic Psychometric Circuit Assessment.
Author Name:James Edward Osler II
Synopsis:

This monograph provides an epistemological rational for the “Multiple Trichotomous Correlation Analysis (identified by the acronym: “MULTRICOR”) post hoc “Triostatistics” (Osler, 2014) test methodology. This paper is part four of the publication entitled, “Trichotomous Charge States: The Novel Trioinformatics Application of Neuroengineering Neuromathematics Notation to Express and Expound Polyphase Electrical Systems and Tri-State Buffers for Digital Circuit Design” that appeared in the Journal on Circuits and Systems. MULTRICOR is an in-depth [Trichotomous Nomographical Variance] statistical procedure for the internal testing of the transformative process of qualitative data into quantitative outcomes through the Tri-Squared Test first introduced in the Journal on Mathematics, and further detailed in the Journal on Educational Technology, Journal on School Educational Technology, and Journal on Educational Psychology. MULTRICOR is an advanced statistical measure that is designed to check the validity and reliability of a Tri-Squared Test that can be used to further verify digital circuit designs. This is a novel approach to advanced statistical post hoc Tri- Squared data analysis. It adds considerable value to the mixed methods approach of research design that involves the holistic combination and comparison of qualitative and quantitative data outcomes. A sequential MULTRICOR mathematical model is provided that illustrates the entire process of advanced statistical Trichotomous inquiry.

Parallel Prefix Adder Using Static Conventional Logic Gates.

Vol. 3  Issue 4
Year: 2015
Issue:Sep-Nov
Title:Parallel Prefix Adder Using Static Conventional Logic Gates.
Author Name:D. Divya, M. Bharathi and C. Ruth Vinutha
Synopsis:

An adder is a device, that adds two numbers and generates the summed result. In digital circuits, there are so many adders like carry select adder, ripple carry adder, carry skip adder, ling adder, manchester carry-chain adder and so on. Among all adders, parallel prefix adder is a highly-efficient binary adder. These parallel prefix adders are implemented in a new topology called Static Null Conventional Logic (NCL) gates. NCL gates are asynchronous circuits which are independent of the clock skew problem, delay and consumes less power. The static implementation of conventional versions of NCL gates use a set of extra minimum-sized transistors to cut off connections to the power rails in specific nodes while the gate is switching. Implementation of parallel prefix in NCL gates, increase the area overhead problems that occur, but the power consumption reduces due to connecting and disconnecting of the specified gate terminal.

A Survey on Brent-Kung, Han-Carlson and Kogge-Stone Parallel Prefix Adders for Their Area, Speed and Power Consumption

Vol. 3  Issue 4
Year: 2015
Issue:Sep-Nov
Title:A Survey on Brent-Kung, Han-Carlson and Kogge-Stone Parallel Prefix Adders for Their Area, Speed and Power Consumption
Author Name:C. Ruth Vinutha, M. Bharathi and D. Divya
Synopsis:

The Parallel Prefix Adder (PPA) is one of the fastest type of adders that had been created and developed from carry look ahead adders. Three common types of parallel prefix adders are Brent-Kung, Han-Carlson and Kogge-Stone adders. This research involves an investigation of the performances of these three adders in terms of computational delay, Power, Speed and design area. The investigation and comparison for these adders was conducted for a 16 bit size. By using the Xilinx 14.5 design software, the designs for Brent Kung, Han-Carlson and Kogge Stone adders were developed. Comparison of area, delay, speed and area for 16 bit Kogge Stone, Han-Carlson and Brent Kung adders show that the Kogge Stone adder is best in terms of speed and the reduced area is obtained from the Han-Carlson adder. The results and simulation are verified using Xilinx 14.5 software.

Performance Analysis of Wind Turbines with DFIG for Low Voltage Ride Through Capability Using a Crowbar Device

Vol. 3  Issue 4
Year: 2015
Issue:Sep-Nov
Title:Performance Analysis of Wind Turbines with DFIG for Low Voltage Ride Through Capability Using a Crowbar Device
Author Name:Mitali Gupta and Ashok Kumar Pandey
Synopsis:

Now-a-days, the penetration level of the wind generator system directly connected to the power system grid is rapidly increasing. Doubly Fed Induction Generator has been broadly used in Variable-Speed Constant-Frequency (VSCF) wind energy generation systems. The Doubly Fed Induction Generator (DFIG) based wind turbine system provides considerably better power delivery towards the demand. In this paper, the performance of DFIG based WT system during various types of symmetrical and unsymmetrical fault has been discussed. LVRT capability of the system based on the grid connection requirement during these faults is studied and discussed here. In this paper, a Crowbar protection device is discussed to overcome the undervoltage and overcurrent phenomenon.

Performance Analysis of Fly-Back Converter Using Photovoltaic Cells

Vol. 3  Issue 4
Year: 2015
Issue:Sep-Nov
Title:Performance Analysis of Fly-Back Converter Using Photovoltaic Cells
Author Name:Vikash Kumar Rai and Krishna Pratap Singh
Synopsis:

Solar energy systems based on photovoltaic (PV) cells have attracted a considerable interest in recent years due to their free and easily available nature and promise related clean energy. Non-renewable energy resources like coal, nuclear, petroleum gas, diesel, etc., are depleting and hazardous to our environment too. There are two types of converter techniques used in the photovoltaic system, first is the single-stage converter technique and second is the two-stage converter technique. This two-stage converter technique uses photovoltaic cells. In the first stage, a fly-back DC to DC converter is used, while in the second stage, are SPWB based inverter is used. Its performance is discussed and compared with the boost converter based photovoltaic cell, for which MPPT based photovoltaic cells are used. For achieving better performance, a Sinusoidal Pulse Width Modulation (SPWM) technique is also used.

Trichotomous Charge States: The Novel Trioinformatics Application of Neuroengineering Neuromathematics Notation to Express and Expound Polyphase Electrical Systems and Tri-State Buffers for Digital Circuit Design

Vol. 3  Issue 4
Year: 2015
Issue:Sep-Nov
Title:Trichotomous Charge States: The Novel Trioinformatics Application of Neuroengineering Neuromathematics Notation to Express and Expound Polyphase Electrical Systems and Tri-State Buffers for Digital Circuit Design
Author Name:James Edward Osler II
Synopsis:

The narrative in this discourse provides the third part of an epistemological rational for the novel discipline of “Trioinformatics”. This novel application of trioinformatic notation in mathematical form is the continuation of the Trioinformatics article that appeared in the March–May i-manager’s Journal on Circuits and Systems,“Trichotomous Charge States” [denoted by the acronym “TCS”] use “Neuroengineering Neuromathematics Notation” as the explicative expression of Trioinformatics in “Polyphase Electrical Systems” and electronic “Tri–State Buffers”. Trioinformatics Neuroengineering also has broad applications when used as an innovative way of explaining the transition from trichotomous logic (Osler, 2015) into trichotomous Triple–I (Osler, 2013d) research questions and associated instrumentation [first introduced in the i-manager’s Journal on Mathematics as a part of the Tri–Squared Test (Osler, 2012a)]. Trioinformatics is an in–depth way of symbolically illustrating the law of trichotomy and a mathematically–grounded rational technique for explaining the ternary properties of electronic circuitry (Osler, 2015). The use of Trioinformatics also adds value to investigative inquiry through the efficacy of digital instruments and tools via eduscientifically–engineered (Osler, 2013) research designs (Osler, 2015). Additional research into trioinformatics and its neuroengineered neuromathematical notation will further advance in–depth investigations into the tripartite aspects of digital instrumentation and digital / electronic circuitry.

A Review on Control Strategy of Wind Turbine With DFIG For Low Voltage Ride Through Capability

Vol. 3  Issue 3
Year: 2015
Issue:Jun-Aug
Title:A Review on Control Strategy of Wind Turbine With DFIG For Low Voltage Ride Through Capability
Author Name:Mitali Gupta and Ashok Kumar Pandey
Synopsis:

Wind energy is a substantial source of renewable energy which has a potentiality of generating energy on a large scale. Developing this new technology becomes more demanding as variable speed wind turbine is highly efficient than the fixed one. DFIG is widely used in variable speed constant frequency wind energy generation system. These type of machines are controlled with the power converters connected to the rotor, where the controlled power is only a portion, approximately equal to the slip of the stator power. DFIG consists of an asynchronous machine, in which the stator is directly connected to the grid and the rotor is connected to the grid via two power electronic converters (back-to-back converter). This characteristic of DFIG has increased the wind energy penetration, but it is more prone to the electrical grid disturbances. This paper provides a review for the protection and control strategy to enhance the LVRT ability of a wind turbine driven DFIG. In this paper, three LVRT methods for protection of DFIG during low voltage events are explained. The three methods are crowbar, DC chopper, series dynamic resistances, and also two hybrid methods named DC chopper with crowbar and DC chopper with series dynamic resistance respectively

Multi Input Single Output Biquadratic Universal Filter using OTRA.

Vol. 3  Issue 3
Year: 2015
Issue:Jun-Aug
Title:Multi Input Single Output Biquadratic Universal Filter using OTRA.
Author Name:Romita Mullick, Neeta Pandey and Rajeshwari Pandey
Synopsis:

This paper proposes a Multi Input Single Output (MISO) voltage-mode universal biquadratic filter employing Operational Transresistance Amplifier (OTRA) as anactive element. All five standard filter functions namely Low Pass(LP), High Pass(HP), Band Pass(BP), Band Reject (BR) and All Pass (AP) are realized from the same circuit topology through appropriate input selections. The quality factor of the proposed configuration can be controlled independent of the angular frequency. Internally grounded input terminals of OTRA, render the proposed circuit insensitive to parasitic capacitances. The effect of non-ideal behaviour of the OTRA on the circuit performance is also analysed. Workability of the proposed filter is verified through SPICE simulations using 0.5 μm CMOS process parameters and the simulation results are in close agreement to the theoretical values. 

Fault Analysis of Stationary and LFM Signals Using Wavelet Transform

Vol. 3  Issue 3
Year: 2015
Issue:Jun-Aug
Title:Fault Analysis of Stationary and LFM Signals Using Wavelet Transform
Author Name:A.NagaJyothi and M.Rajeswari
Synopsis:

The fault analysis of sine and linear frequency modulated signals using wavelet transform is proposed in this paper. By using the wavelet transform, the time-frequency localization characteristics and the frequency information of waveform can be integrally obtainable. This approach is more efficient in monitoring the time-varying disturbances when compared with those of fourier transform based methods. In this paper, the result analysis shows how the decomposition of sine and linear frequency modulated signals has been carried out by using wavelet transform.

An Optimized and Cost Efficient Realization of Reversible Braun Multiplier

Vol. 3  Issue 3
Year: 2015
Issue:Jun-Aug
Title:An Optimized and Cost Efficient Realization of Reversible Braun Multiplier
Author Name:Neeta Pandey, Nalin Dadhich and Mohd. Zubair Talha
Synopsis:

In CMOS logic, there is a steady increase in power dissipation which appears in the form of heat to the surrounding environment and affects the reliability. The research efforts are made towards looking into alternatives that go beyond the traditional CMOS technologies, and reversible logic has emerged as a promising choice. In this paper, an optimized and cost efficient realization of reversible Braun multiplier is presented. The design of a 4x4 bit multiplier is developed, designed and presented in this paper as an illustration. The architecture is iterative and hence this can easily be extended to the generalized multiplier of any order. The proposed design of a 4x4 reversible Braun multiplier uses three types of reversible gates namely, PG, HNG and TG gates. The proposed design is compared with an already presented reversible multiplier design showing that the proposed multiplier design is more efficient in terms of quantum cost, constant inputs, garbage outputs and the number of elementary reversible gates.

Neuroengineering Neuromathematics Notation: The Novel Trioinformatics System that Defines, Explains, and Expresses the Research Application of the Law of Trichotomy for Digital Instrumentation and Circuit Design

Vol. 3  Issue 3
Year: 2015
Issue:Jun-Aug
Title:Neuroengineering Neuromathematics Notation: The Novel Trioinformatics System that Defines, Explains, and Expresses the Research Application of the Law of Trichotomy for Digital Instrumentation and Circuit Design
Author Name:James Edward Osler II
Synopsis:

This paper provides the second part of an epistemological rational for the novel discipline of “Trioinformatics”. This novel extension of notation in mathematical form is the continuation of the Trioinformatics article that appeared in the imanager Journal on Circuits and Systems.“Neuroengineering Neuromathematics Notation” is the collaborative and comprehensive expression of Trioinformatics as a sequential sequence of inquiry into a precise research analysis methodology. Neuroengineering is an innovative way of explaining the transition from trichotomous logic (Osler, 2015) into trichotomous Triple–I (Osler, 2013d) research questions and associated instrumentation [first introduced in the imanager Journal on Mathematics as a part of the Tri–Squared Test (Osler, 2012a)]. Trioinformatics is an in–depth way of symbolically illustrating the law of trichotomy and a mathematically–grounded rational technique for explaining the ternary nature of electronic circuitry (Osler, 2015). The use of the Trioinformatics also adds value to investigative inquiry through the efficacy of digital instruments and tools via eduscientifically–engineered (Osler, 2013) research designs (Osler, 2015). Additional research into trioinformatics via the use of neuroengineered neuromathematical notation will further advance in–depth investigations into the tripartite aspects of nature and natural phenomena.

Performance Analysis of Various Techniques on 6T SRAM Cell.

Vol. 3  Issue 2
Year: 2015
Issue:Mar-May
Title:Performance Analysis of Various Techniques on 6T SRAM Cell.
Author Name:Pushpa Raikwal, Vaibhav Neema and Ajay Verma 
Synopsis:

Leakage current has been a major issue in system on chip designs with sub-micron technologies. For 180nm and below technologies, leakage is the main factor which dominates over the dynamic power and contributes to almost or more than 40% of total power dissipation. Thus it become very important to control the leakage current. This paper presents the effect of several techniques based on leakage reduction mechanism such as stacking effect and sleepy stack transistors on standard 6-T SRAM cell. Also their comparative analysis has been carried out on the basis of leakage current, propagation delay, static noise margin (SNM) and dynamic power dissipation. The produced result depicts SRAM cell with stack technique shows 16.65%increase in propagation delay, whereas sleepy stack SRAM shows 32.83% reduction in delay as compare to basic 6T SRAM cell. When we discuss about dynamic power dissipation 6T SRAM cell with stack technique consumes 39% more, but sleepy stack cell(in sleep mode) dissipates 17.61% reduced and sleepy stack cell (in active mode)dissipates 10.47% less power as compare to basic 6T SRAM cell.

About leakage current, it can be seen that 6T SRAM cell with stacking effect shows 86% less leakage flowing through the NMOS transistor whereas in PMOS transistor the leakage current got reduced to 99.94% as compare to basic 6T SRAM cell. When we come to sleepy stack technique the leakage current flowing through the NMOS cell increases by 111%, where there is a small difference in leakage of PMOS as compare to leakage of PMOS of 6T SRAM cell. Tools Used: TANNER EDA for schematic simulation, The simulation technology used is TSMC 180nm.