Performance Analysis of Adder Circuits Using FINFET'S

Volume 5 Issue 3 June - August 2017

Research Paper

Performance Analysis of Adder Circuits Using FINFET'S

Nancharaiah Vejendla* , R. Ramana Reddy**, N. Balaji***

* Research Scholar, Department of Electronics and Communication Engineering, JNTU Kakinada, India.

** Professor and Head, Department of Electronics and Communication Engineering, MVGR College of Engineering (A), Viziangaram. India.

*** Professor and Vice-principal, Department of Electronics and Communication Engineering (Admin), UCOE Narasaraopeta, JNTUK, India

Vejendla, N., Reddy, P. R., Balaji, N. (2017). Performance Analysis of Adder Circuits Using FINFET'S. i-manager’s Journal on Circuits and Systems, 5(3), 1-9. https://doi.org/10.26634/jcir.5.3.13811

Abstract

Due to scaling of conventional MOS transistors, leakage currents are increasing which leads to increase in power dissipation. Increase in power dissipation puts limit on scaling. To overcome the power dissipation problem, conventional MOS transistors are replaced with FinFETs. FinFETs have low leakage currents which reduce power dissipation. In this paper the focus is on the implementation of different full adder circuits using FinFETs. Comparisons are made between CMOS and FinFET implementation of Hybrid Full Adder, 14 Transistor Full Adder, GDI based Full Adder, and 10 transistor Full Adder using 32 nm and 45 nm technology models. FinFET implementation achieves low power and high speed compared to CMOS implementation.