FPGA Implementation Of Barrel Shifter using Reversible Logic

Vol.2  No.1

Year: 2014

Issue : Dec-Feb

Title : FPGA Implementation Of Barrel Shifter using Reversible Logic

Author Name : S. Justin Alex, T.Antony Beno Prakash , R.Anandarasu , S.Poorna Lekha , Komala Vani Chala

Synopsis :

Conventional Combinational logic circuits dissipate heat for every bit of information that is lost during their operation. Due to this fact the information once lost cannot be recovered in any way. A reversible logic gate is a n-input, n-output logic device which helps to determine the outputs from the inputs but also the inputs can be recovered from the outputs. Extra inputs or outputs are added so that the number of inputs is made equal to the number of outputs whenever it is necessary. For reversible computer the heat dissipation is logically 0. Therefore, in upcoming high performance it is considered as the promising technology at low power consumption. Therefore, there is requirement of designing reversible gates. A barrel shifter is a digital circuit that can shift a data word by a specified number of bits in one clock cycle. The proposed techniques overcome the shortcoming of the present techniques like garbage output, delay and quantum cost and efficiency in designing the circuit which can be performed effectively by increasing the performance and reducing the delays with the same power consumption. It also reduces the no of flip flops, and gates which reduces the memory size and area.

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Synchronous Reference Scheme for Improving the Active Power Filter Performance by using Fuzzy Controller

Vol.2  No.1

Year: 2014

Issue : Dec-Feb

Title : Synchronous Reference Scheme for Improving the Active Power Filter Performance by using Fuzzy Controller

Author Name : Appikonda mohan, BOLISETTI NAVEEN, Chiranjeevi Tirumalasetty , MOTHI RAM bhukya

Synopsis :

This paper suggests an active power filter implemented with a four leg voltage-source inverter using DQ (Synchronous Reference Frame) based Current Reference Generator scheme. The use of a four-leg voltage-source inverter allows the compensation of current harmonic components, as well as unbalanced current generated by single-phase non-linear loads. The grid interfacing can thus be utilized as:1) Power Converter to inject power generated from rest of the grid, and 2) Shunts APF to current unbalance, load current harmonics and load reactive power demand. The compensation, performance of the proposed active power filter using an adaptive fuzzy controller and the associated control scheme under steady state and transient operating conditions are demonstrated through simulation results.

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An improved Multilevel Inverter with Lesser Number of Switches for aAn Induction Motor Drive

Vol.2  No.1

Year: 2014

Issue : Dec-Feb

Title : An improved Multilevel Inverter with Lesser Number of Switches for aAn Induction Motor Drive

Author Name : Ayyappa Srinivasan M G, N.Nirmal Singh

Synopsis :

An improved three level inverter scheme, with less number of switches, having the features of common mode voltage elimination, DC link capacitor voltage balancing, and minimization and equalization of voltage stress across the switches, for an open end winding induction motor drive, have been proposed in this paper. Open-end winding induction motor, when fed from its two ends by a three level inverter, suffers from the drawbacks of common mode voltage, which causes current to flow through its bearings along with the shaft and that type of capacitor voltage unbalance, causes current to flow through the neutral point. Further, such inverters require a large number of switches, which lead to higher switching losses and unequal voltage stress in the switches. A new inverter topology with less number of switches, that gets rid of the problems of common mode voltage and DC link capacitor voltage unbalance along with reduced and equalized voltage stresses in the switches, has been proposed in this paper. The simulation and the hardware results of the proposed topology show smoother output voltages across the machine phases.

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Fuzzy Based Power Flow Control in Grid connected Microgrid Consistingo of Pv-Pemfc Hybrid System

Vol.2  No.1

Year: 2014

Issue : Dec-Feb

Title : Fuzzy Based Power Flow Control in Grid connected Microgrid Consistingo of Pv-Pemfc Hybrid System

Author Name : MOTHI RAM bhukya, BOLISETTI NAVEEN, Chris Fook Sheng NG, Ch.Ravi Kumar

Synopsis :

This paper evaluates the performance of a fuzzy based power flow control of grid connected hybrid system. The hybrid system composed of a Photo Voltaic (PV) array and a Proton Exchange Membrane Fuel Cell (PEMFC) is considered. The Photo Voltaic (PV) array normally uses a Maximum Power Point Tracking (MPPT) technique to continuously deliver the highest power to the load when there are variations in irradiation and temperature which make it become an uncontrollable source. In coordination with PEMFC, the hybrid system output power becomes controllable. Two operation modes, the Unit -Power Control (UPC) mode and the Feeder-Flow Control (FFC) mode, can be applied to the hybrid system. In the UPC mode, variations in load demand are compensated by the main grid because the hybrid source output is regulated to reference power by using an adaptive fuzzy controller. The proposed operating strategy with a flexible operation mode change always operates the PV array at maximum output power and the PEMFC in its high efficiency performance band, thus improving the performance of system operation, enhancing system stability, and decreasing the number of operating mode changes. This new control concept is demonstrated with extensive MATLAB/Simulink simulation studies.

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Electronic Circuit Design for Electromagnetic Compliance through Problem-Based Learning

Vol.2  No.1

Year: 2014

Issue : Dec-Feb

Title : Electronic Circuit Design for Electromagnetic Compliance through Problem-Based Learning

Author Name : Gisli Thorsteinsson, Tom Page

Synopsis :

Recent regulations have demanded that electronics manufacturing companies control emissions from their products and the susceptibility of their products for Emissions from other products. In addition, unexpected product failure and the ever-present demands of technology are also forcing the electronics industry to face the need to maintain Electrical Integrity. The investigations into high-speed design techniques have shown three major causes of failure: emissions from interconnecting conductors; poor PCB layout and lack of technical knowledge in Electro Magnetic Compatibility (EMC). Catching these kinds of electrical integrity problems early in the design phase allows designers to take timely action without jeopardising project time scales. The work reported here presents design for manufacturing guidelines and rules to maintain electrical integrity in Printed Circuit Boards (PCBs). Currently, a common method for handling EMC is through compliance testing of the final product. Similarly, noise budget is measured on finishing prototypes. Since product life cycles are reduced, dealing with EMC late in the design cycle is undesirable. The cost of fixing may also be higher at a final stage because only a few options are available to correct the problem. A 'find and fix' approach is no longer acceptable. More and more companies are facing or will soon be facing EMC and electrical integrity issues. The majority of analysis tools available today are targeted towards simulation engineers. Such tools are not easy to use and are dependent on the availability and accuracy of complex simulation models. Moreover, they also tend to be ineffective on how to correct potential EMC problems.

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A Design and Real Time Implementation of Plc for Automatic Neutralization in ASTP

Vol.1  No.4

Year: 2013

Issue : Sep-Nov

Title : A Design and Real Time Implementation of Plc for Automatic Neutralization in ASTP

Author Name : P. Premkumar, R.Dhanasekar , G.R.Hamsa , S.K.Logadharshini , S.Elavarasan

Synopsis :

The paper introduces a Real Time monitoring Automatic analysis and Neutralization of HNO3 in Acid Storage and Treatment Plant (ASTP). This system aims to reduce the variability and processing time involved in manual neutralization while maintaining comparable results. The used acids like HNO , HF are acidic that causes environment hazards so it 3 should be treated properly. The conventional method employs sampling the acid for pH measure and then manually neutralizes it. This system proposes pH monitoring at running condition and neutralizing with lime automatically so as to maintain pH level at 6.5 to 8.0. and also the whole plant with various parameters like lime milk level, pressure, temperature, flow of acid will be monitored integrally and automatically by the implementation of PLC.

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Computer Assisted System for the Autistic Children

Vol.1  No.4

Year: 2013

Issue : Sep-Nov

Title : Computer Assisted System for the Autistic Children

Author Name : K.Kiruba, Dr.D.Sharmila , K.Suganya , K.Sowmya

Synopsis :

Autistic children lack communication and socialization showing stereotyped behavior. This paper is emphasizing on a hardware and a software to identify the needs of such children and also to provide speech therapy. Software has been designed to engage the child throughout the day and helps the parents to identify their needs. In the hardware technique vocal status is tracked from the neck by measuring the glottal airflow estimates. Clinically the treatment can be enhanced by making the child to speak continuously via a biofeedback.

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Subthreshold Leakage reduction Strategies for the Design of Low Power Sram

Vol.1  No.4

Year: 2013

Issue : Sep-Nov

Title : Subthreshold Leakage reduction Strategies for the Design of Low Power Sram

Author Name : Vanitha, Parimaladevi M , Sharmila D

Synopsis :

The intensifying trade of transportable electronic devices such as cell phones, laptops, tablet PCs and other handheld devices require minimum power dissipation for retaining the battery life, high reliability and compactness of the system. The highly energy efficient processors and handheld portable systems involve SRAMs as the crucial components which indicate that significant notice has to be given in designing the high performance and power reduced SRAMs. The consumption of power and area penalty of SRAM(Static Random Access Memory) reaches a higher value accordingly with the scaling down of technology. This Paper mainly deals with the subthreshold leakage current which is the predominant leakage component of SRAM cell and circuit level leakage reduction techniques to obtain subthreshold leakage reduced SRAM cell. Various SRAM cell topologies are summarized in the point of subthreshold leakage reduction and their subthreshold and gate leakage currents Hold SNM at various temperatures and process the corners which have been measured and compared. Simulations are performed with 90nm CMOS technology process file using Mentor Graphics. Finally, the 8T SRAM bitcell has been identified as the best cell topology designed with dynamic V DD scaling technique, which reports considerable leakage reduction over 6T at all process corners. Simulation results revealed that there is a considerable improvement of hold SNM at 25ºC in 8T over other SRAM cell topologies.

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Reduced Wirelength-Based Low Power Performance of Multibit Flip-Flop

Vol.1  No.4

Year: 2013

Issue : Sep-Nov

Title : Reduced Wirelength-Based Low Power Performance of Multibit Flip-Flop

Author Name : M.Karthick, S.Vijayakumar

Synopsis :

Power reduction is a main parameter to design VLSI circuits. In this paper, to design a number of D-flip flop performing at the same time, the given clock signal is reduced using multi bit flip-flop. The multi bit flip flop is mainly used to improve the clock power for the given common clock signal and to reduce the switching power. This method is performed to replace some D flip-flop into multi bit flip-flops with the given common clock input. In this proposed technique, first step is to identify the flip flops and its placed location, second step is to build the combination table mainly by merging the flip flop and removing the unwanted merging flip-flops, final step is to assign the region , place the flip flop in these flip-flops merging and replacing the merging location. By using this method, the result is used to reduce the power to 24mW and area by reducing to 35 gate count ,because this method considers the area measured as the number of gate count in the merging flip flop.

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Differently Paired Current Feedback for Common Mode Stability in High Performance Two Stage CMOS Amplifiers

Vol.1  No.4

Year: 2013

Issue : Sep-Nov

Title : Differently Paired Current Feedback for Common Mode Stability in High Performance Two Stage CMOS Amplifiers

Author Name : Guanglei An, Chris Hutchens, Robert.L.Renneker II

Synopsis :

A robust method for stabilizing Fully Differential (FD) two stage amplifiers is presented in Figure 2(c) which is fast, guaranteed latch free, low offset while offering simpler tracking of compensation with some increase in power dissipation. Submicron processes with supply voltages ranging from 0.7 to 1.2 V place an ever increasing demand for efficient use of analog supply budget headroom, Common Mode (CM) offset (VOSCM ), differential offset (Vos), and noise erode dynamic range. Common Mode (CM) offset is an often overlooked error contribution of the CM feedback amplifier. The desirable qualities of a CM amplifier are, fast settling, latch up free operation under all transient conditions while being low power, contributing low noise, low VADCs to FD circuits, i.e. pipeline  (Analog-to-Digital Convertors). It  is widely known that, current feedback can be fast, limited only by the current gain bandwidth of the process [1,2]. The proposed CM current amplifier in Figure 2(c) avoids latching states while maintaining Common Mode FeedBack (CMFB) loop stability and simplifying CMFB compensation.

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Analysis of Memristor Based Circuits

Vol.1 No.3

Year : 2013

Issue : Jun-Aug

Title : Analysis of Memristor Based Circuits

Author Name : Durga.M, U.K. Sathiskumaar

Synopsis :

In almost all of the currently working circuits, especially in analog circuits implementing signal processing applications, basic arithmetic operations such as multiplication, addition, subtraction and division are performed on values which are represented by voltages or currents. However, in this paper, we propose a new and simple method for performing analog arithmetic operations, by which in this scheme, signals are represented and stored through a memristance of the newly found circuit element, i.e. memristor, instead of voltage or current. Some of these operators such as divider and multiplier are much simpler and faster than their equivalent voltage-based circuits and they require less chip area. In addition, a new circuit is designed for programming the memristance of the memristor with predetermined analog value. Presented simulation results demonstrate the effectiveness and the accuracy of the proposed circuits.

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PC Cooling fan using Pulse Width Modulation

Vol.1 No.3

Year : 2013

Issue : Jun-Aug

Title : PC Cooling fan using Pulse Width Modulation

Author Name : K.V.N. Kavitha

Synopsis :

The main objective of this paper is to design a circuit that can control the speed of a fan based on the ambient temperature. The fan is used for preventing the heat problems faced while using high graphics in a laptop or PC. The speed of the fan is varied based on the pulses that the timer sends out and the concept of pulse width modulation is used. This provides a simple and inexpensive way to protect systems like a computer from overheating. The existing external PC cooling fans have a higher energy consumption than the proposed model. This model is temperature controlled and the motor is powered on and off based on the pulsed output from the Pulse Width Modulator (PWM) generator circuit which invariably depends on the temperature. Hence the model provides cooling based on the need rather than continuously.

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Power Efficient Functional Units for High Speed Computations

Vol.1 No.3

Year : 2013

Issue : Jun-Aug

Title : Power Efficient Functional Units for High Speed Computations

Author Name : B.Dinesh, R.Jagadeesh , Dr.M.Kathirvelu

Synopsis :

Power consumed per unit switching activity in a CMOS based computational unit is greatly dependent on the power consumption of the sum and carry generation units. This paper is focussed on reducing area and PDP of the computational units through gate level and transistor level optimisation. At transistor level 6T Mux based CMOS-CPL XOR gates with stable rise and fall times are used. The concept of gate level Boolean equivalent substitution is used in optimization of logics used in carry generation in a computational unit. Optimised carry block exhibits 50% lesser delay and 45% lesser power consumption compared to a ANDOR based carry generation system. An optimized computational unit at layout level is realised with proposed logical substitutions and with Mux based XOR gates. The resulting computational unit exhibits 60% reduced power consumption compared to a standard realisation. Synthesis of layout and simulations are done by using 45nm technology.

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IGBT Based Power Evacuation using Ac Segmented Transmission Lines

Vol.1 No.3

Year : 2013

Issue : Jun-Aug

Title : IGBT Based Power Evacuation using Ac Segmented Transmission Lines

Author Name : D.Gowthami, Tharanisrisakthi , J.Shibu

Synopsis :

Emerging countries like India, China suffer a huge problem of power crisis. The main reason for this is, power evacuation. The inability of bulk power evacuation with the present mode of transmission (HVAC & HVDC) leads us to a concept called B2B segmented AC transmission. B2B segmented AC transmission consists of a rectifier and inverter unit by using IGBT. With the advent of advanced power electronics devices, the authors are able to reduce the size and complexity of converters with increase in power ratings. By using this method the limitation of HVDC can be overcome which makes us to evacuate bulk power to longer distance with less loses. In this paper they use IGBT (Insulated Gate Bipolar Transistor) as B2B converter for transmission lines used to transmit large blocks of energy from long distance generating plants or to connect areas of large th power system. Taking a real time problem published in The New Indian Express on July 20 ,2011 which indicates power evacuation problem existing in Tamilnadu wind power sector, the authors present this paper.

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A Two Stage Power Optimized Implantable Neural Amplifier Based on Cascoded Structures

Vol.1 No.3

Year : 2013

Issue : Jun-Aug

Title : A Two Stage Power Optimized Implantable Neural Amplifier Based on Cascoded Structures

Author Name : GuangleiAn, Chris Hutchens, Robert.L.Renneker II

Synopsis :

A low power, low noise of the two stage neural amplifier used in an intelligent Radio-Frequency Identification (RFID) based on folded cascode Operational Transconductance Amplifier (OTA) is presented. The optimization of the number of amplifier stages are discussed to achieve the minimum power and area consumption. The amplifier was submitted for fabrication in a 0.18 μm CMOS process. The amplifier power supply is 0.7V. The midband gain of amplifier is 58.4dB with a 3dB bandwidth from 0.71 to 8.26 kHz. Measured input-referred noise and total power consumption are 20.7μV rms and 1.90 μW respectively. The measured result shows that optimizing the number of stages can achieve lower power consumption and demonstrates the neural amplifier's suitability for instu neutral activity recording.

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