Double Node Upset Radiation Immune Latch Design in 65 nm CMOS Technology

Volume 6 Issue 3 June - August 2018

Research Paper

Double Node Upset Radiation Immune Latch Design in 65 nm CMOS Technology

Sandhya Kesharwani* , Vaibhav Dedhe**

* PG Scholar, Department of Electronics and Telecommunication, Shri Shankaracharya Technical Campus, Chhattisgarh, India.

** Assistant Professor, Department of Electronics and Telecommunication, Shri Shankaracharya Technical Campus, Chhattisgarh, India.

Kesharwani, S., and Dedhe, V. (2018). Double Node Upset Radiation Immune Latch Design in 65nm CMOS Technology. i-manager’s Journal on Circuits and Systems, 6(3), 21-27. https://doi.org/10.26634/jcir.6.3.14624

Abstract

The space environment is characterized with various energetic particles like cosmic rays, cosmic neutrons, alpha particles and heavy ions from solar flares. Nowadays most of the circuits used in space applications are being made of Complementary Metal Oxide Semiconductor (CMOS). The technology is scaling down, i.e. reduction in supply voltage and node capacitances lead to decrease of amount of charge stored on a node, which makes the circuit more vulnerable towards particle induced charge. When amount of this particle induced charge is high enough, a transient fault appears like a glitch called as Single Event Transient (SET). As the feature size scales down, the vulnerability of circuits to radiation induced error has also been increased, as this may cause Double Node Upset (DNU) i.e Single Event Double Node Upset (SEDU). In this paper, some of the best known designs to mitigate the Single Event Upset as well as Single Event Double Node Upset in 65 nm CMOS technology using standard TSPICE tool has been discussed. The comparison of those designs on the same platform i.e 65 nm technology is presented, their power consumption and propagation delay are also compared.