A High Speed Arithmetic Architecture of Parallel Multiplier-Accumulator (MAC) Based on Radix-2 Modified Booth Algorithm

Volume 5 Issue 3 June - August 2017

Research Paper

A High Speed Arithmetic Architecture of Parallel Multiplier-Accumulator (MAC) Based on Radix-2 Modified Booth Algorithm

Ishita Verma* , Priyanka Ghosh**, Upendra Soni***, Dharmendra Singh****

*-** UG Scholar, Department of Electronics and Telecommunication Engineering, Shri Shankaracharya Institute of Professional Management and Technology (SSIPMT), Bhilai, India.

***-**** Assistant Professor, Department of Electronics and Telecommunication Engineering, Shri Shankaracharya Institute of Professional Management and Technology (SSIPMT), Bhilai, India.

Verma, I., Ghosh , P., Soni, U., and Singh, D. (2017). A High Speed Arithmetic Architecture of Parallel Multiplier-Accumulator (MAC) Based on Radix-2 Modified Booth Algorithm. i-manager’s Journal on Circuits and Systems, 5(3), 38-42. https://doi.org/10.26634/jcir.5.3.13866

Abstract

In this paper, a new architecture is proposed for multiplier and Accumulator to increase the arithmetic operation. Multiplication and accumulation will help in improving the performance of multiplier. The Radix-2 modified booth algorithm is used for the reduction of partial products. The parallel multiplier can be such as radix 2 modified booth algorithm is used to improve the computations; this can be achieved using fewer adder and steps. By using Radix-2 modified booth multiplier algorithm the high speed of operation can be achieved.