FPGA Implementation of Reversible High-Speed Carry Skip Adder and Carry Skip BCD Adder

Volume 6 Issue 1 December - February 2018

Research Paper

FPGA Implementation of Reversible High-Speed Carry Skip Adder and Carry Skip BCD Adder

K. Rajesh * , G. Umamaheswara Reddy**

* Research Scholar, Department of Electronics and Communication Engineering, Sri Venkateswara University, Tirupati, Andhra Pradesh, India.

** Professor, Department of Electronics and Communication Engineering, Sri Venkateswara University, Tirupati, Andhra Pradesh, India.

Rajesh, K., and Reddy, G. U. (2018). FPGA Implementation of Reversible High-Speed Carry Skip Adder and Carry Skip BCD Adder. i-manager’s Journal on Circuits and Systems, 6(1), 14-19. https://doi.org/10.26634/jcir.6.1.14496

Abstract

One of the most promising and emerging technologies in the low power VLSI is reversible logic computing, which has found its voluminous applications in nanotechnology, Quantum computing (Feynman,1986), and Quantum Dot Cellular Automata (QCA). This study presents high-speed reversible carry skip adder and carry skip BCD adder. The performance analyses of proposed architectures are mainly focused on the delay and almost all the previous existing designs are not concentrated on the delay. In this paper, both the proposed design architectures are highly optimized in terms of delay. The complete simulation and synthesis process is carried out by using the Xilinx ISE 14.7 and it is dumped on the FPGA Spartan-6.