Implementation of Reversible Logic Gate (Peres Gate) to Design a Half Adder for Low Power with Reduced Area and Improved Efficiency

Volume 6 Issue 3 June - August 2018

Research Paper

Implementation of Reversible Logic Gate (Peres Gate) to Design a Half Adder for Low Power with Reduced Area and Improved Efficiency

Tripti Nirmalkar* , Deepti Kanoujia**, Kshitiz Varma***

* PG Scholar, Department of Electronics and Communication Engineering, Chhattisgarh Swami Vivekananda Technical University,Chhattisgarh, India.

** Post Graduate, Department of Electronics and Communication Engineering, Sri Shankaracharya College of Engineering and Technology, Chhattisgarh, India.

*** Project Officer, Department of Electronics and Communication Engineering, Chhattisgarh Swami Vivekananda Technical University, Chhattisgarh, India.

Nirmalkar, T., Kanoujia, D., and Varma, K. (2018). Implementation of Reversible Logic Gate (Peres Gate) to Design a Half Adder for Low Power with Reduced Area and Improved Efficiency. i-manager’s Journal on Circuits and Systems, 6(3), 36-42. https://doi.org/10.26634/jcir.6.3.14877

Abstract

Research on reversible logic gates has become one of the interesting fields in the world of electronics. This has been proved to be one of the most reliable logics that originates its place in low power CMOS skills, Nano and optical calculation and many more. These broadsheet offers the comparison of different reversible logic gates in expressions of quantum cost, delay, transistor charge, and also implementation of one of the alterable logic gates, i.e. Peres gate in a conventional half adder with the help of an efficient algorithm. The work is performed in Xilinx using Verilog coding. The simulation result shows improved efficiency, low power, and low area consumption as related to the standard half adder. This half adder can be utilized in different applications, where circuit comprising of a conventional half adder can be replaced by Peres Half Adder (HAP).