Domestic Wastewater Reclamation and Reuse in Nigeria: A Case Study of Some Selected Treatment Plants in Abuja and Lagos

Volume 15 Issue 1 August - October 2019

Research Paper

Domestic Wastewater Reclamation and Reuse in Nigeria: A Case Study of Some Selected Treatment Plants in Abuja and Lagos

Olasehinde Samuel Oloruntoba* , Alabi Tobi Michael**

*-** Department of Building, Federal University of Technology, Akure.

Oloruntoba, O. S., & Michael, A. T. (2019). Domestic Wastewater Reclamation and Reuse in Nigeria: A case study of some selected treatment plants in Abuja and Lagos. i-manager’s Journal on Future Engineering and Technology , 15(1), 1-10.

Abstract

The challenges facing the supply of potable water and the environmental nuisance that wastewater discharge is provoking in Nigeria cannot be underestimated. While most of the previous studies focused on industrial wastewater treatment, this study identified the challenges of domestic wastewater reclamation and reuse in Nigeria; assessed the methods of reclaiming domestic wastewater and examined the effects of reclaiming and reusing domestic wastewater in Nigeria with a view to providing information that will enhance the sustainable reuse of wastewater in Nigeria. The study used primary and secondary data. Primary data was collected from seven selected wastewater treatment plants in different geopolitical zones and Abuja municipal. It was sourced using site visits and google forms. Data collected include the challenges of reclaiming domestic wastewater, the method of reclamation, level of treatment operating and current ways of reusing domestic wastewater in their organization/estate, knowledge of domestic wastewater reclamation and reuse, ways in which reclaimed domestic wastewater can be reuse in Nigeria and effects of reclaiming and reusing domestic wastewater in Nigeria. The data were analyzed using frequency, percentages, content analysis and mean score (MS). Finding reveals that the major challenges of wastewater reclamation and reuse in Nigeria are; cost (it is capital intensive), erratic power supply, shortage of skilled personnel, sewage collection problem and ineffective public sewer while the methods of reclamation in use are activated sludge (extended aeration), anaerobic digestion, oxidation ponds and membrane filtration respectively. Furthermore majority of the wastewater treatment plant employed the tertiary level of treatment. The result of mean score showed that the effects of reclaiming and reusing domestic wastewater in Nigeria were to prevent breakout of waterborne diseases (MS=4.93), to prevent environmental pollution (MS=4.88) and rapid urban population growth (MS=4.85). The study also revealed that agricultural purposes should be the major way of reusing wastewater in Nigeria based on the analyzed data .The study concluded that breakout of waterborne diseases and environmental pollution are the major reasons why Nigeria should reclaim and reuse her domestic wastewater.

A Comparative Analysis Report on Modified Reversible Sequential Circuits realized with Improved Quantum cost

Volume 7 Issue 1 December - February 2019

Research Paper

A Comparative Analysis Report on Modified Reversible Sequential Circuits realized with Improved Quantum cost

Gopi Chand Naguboina* , T. Sravya**

* Assistant Professor, Department of Electronics and Communication Engineering, MaharajVijayaramGajapathi Raj (MVGR) College of Engineering (Autonomous), Vizianagaram, Andhra Pradesh, India.

** PG Scholar, Department of Electrical and Electronics Engineering, Sri PadmavatiMahilaVisvavidyalayam, Tirupati, Andhra Pradesh, India.

Naguboina, G. C., and Sravya, T. (2019). Transient Dynamic Finite Element Analysis of Cup Drawing Process. i-manager's Journal on Circuits and Systems , 7(1), 37-50. https://doi.org/10.26634/jcir.7.1.15243

Abstract

Reversible Logic is the dominating field of research in low power VLSI. In recent times, reversible logic has gained special attention in order to reduce power consumption mainly in concern to digital logic design. The main aim of this paper is to give an overall summary report on Digital sequential circuits like Shift registers and Counters designed using reversible logical computation. Digital circuits are the circuits implemented using Boolean logical expressions. Digital circuits find many applications in present daily life. Different types of combinational and sequential circuits are designed using reversible logic to reduce power dissipation. A Boolean function f(i1, i2, i3,……, in) having 'n' inputs and 'm' outputs is said to be logically reversible if the number of inputs are equal to the number of outputs (i.e. n = m) and the input pattern maps uniquely to the output pattern. Few reversible logic gates present in the literature are NOT gate, Feynman Gate (CNOT gate), Double Feynman Gate, Peres Gate, TR gate, Seynman Gate, etc. The reversible gate must run both forward and backward directions such that the inputs can be retrieved with the knowledge of outputs. Reversible Logic has applications in various fields like Quantum Computing, Optical Computing, Nano-technology, Computer Graphics, low power VLSI, etc. Reversible logic has gained essence in recent years largely due to its property of low power consumption and low heat dissipation. Till date in the literature, universal shift register and shift counters are realized using reversible logical computation for the first time in this paper. In this paper, a summary report is given on Sequential circuits like Shift registers and Counters designed using reversible logical computation with improved quantum cost. A comparative study on reversible and irreversible sequential logical circuits is also given. The realized reversible logical circuits are analysed in terms of quantum cost, garbage outputs, number of gates, and propagation delay. The circuits have been designed and simulated using Xilinx software.

Simulation of High Frequency Step Down of Single Phase Matrix Converter as an Universal Converter

Volume 7 Issue 1 December - February 2019

Research Paper

Simulation of High Frequency Step Down of Single Phase Matrix Converter as an Universal Converter

K. V. Divya Sree* , S. K. Ruksana**

* Assistant professor, Department of Electronics and Communication Engineering, Vasavi college of engineering, Hyderabad , Telangana,India.

** PG Scholar, Department of Electronics and Communication Engineering, Vasavi college of engineering, Hyderabad , Telangana,India.

Sree, D. K. V., and Ruksana, S. K. (2019). Transient Dynamic Finite Element Analysis of Cup Drawing Process. i-manager's Journal on Circuits and Systems , 7(1), 30-36. https://doi.org/10.26634/jcir.7.1.15726

Abstract

This paper presents the concept of single phase matrix converter as an universal converter for high frequency step down operation. Matrix converter implemented as an rectifier, chopper, inverter, and cyclo-converter for a high frequency step down has been presented in this paper. This will reduce the need for the new or an extra converter requirement. The technique used for the implementation of the proposed topology was sinusoidal pulse width modulation technique. This paper verifies the four possible conversion processes, such as AC-DC, DC-DC, DC-AC, and AC-AC from a high frequency input to the desired low frequency output by the single phase matrix converter alone. The results of the four conversion topologies along with the filter has been presented in this paper. The proposed topology has been implemented in the Matlab / Simulink software and the desired results for each of the converter topology has been verified.

High Speed and Low Power 4*4 Array Multiplier Design

Volume 7 Issue 1 December - February 2019

Research Paper

High Speed and Low Power 4*4 Array Multiplier Design

N. Suresh* , K. S. Shaji**, M. Chaitanya Kishore Reddy***

*_** Professor, Department of Electronics and Communication Engineering, Sphoorthy Engineering College, Hyderabad, Telangana, India.

*** Professor, Department of Computer Science Engineering, Sphoorthy Engineering College, Hyderabad, Telangana, India.

Suresh,N., Shaji, K. S., and Reddy, M. C. K. (2019). High Speed and Low Power 4*4 Array Multiplier Design. i-manager's Journal on Circuits and Systems , 7(1), 24-29. https://doi.org/10.26634/jcir.7.1.15530

Abstract

The main objective of this research is to design a Low power 4*4 Array Multiplier using modified GDI based full adder techniques, which consumes low power and have high speed computation compared to the CMOS technology. The modification has implemented in full adder design using GDI techniques in which the logical circuit reduces the number of transistors in the overall schematic. As we design any types of multiplier, the main logical block is adder and AND gate, similarly in this research also the authors concentrate to design Low power 4*4 Multiplier, which contains 8 full adder blocks. In these blocks, a modified GDI based full adder technology has been introduced. This way of reducing the number of transistors reduces the power consumption of overall circuits, propagation delay, and surface area. At the same time, the computation speed of the multipliers is increased.

Features of PSO – BFOA Based Increment Conductance Method with FPGA

Volume 7 Issue 1 December - February 2019

Research Paper

Features of PSO – BFOA Based Increment Conductance Method with FPGA

Ch. Venkateswara Rao* , S. S. Tulsiram**, B. Brahmaiah ***, Ch. Ramya****

* Lecturer, Department of Electrical and Electronics Engineering, Salalah College of Technology, Salalah, Oman.

** Dean and Professor, Department of Electrical and Electronics Engineering, Salalah College of Technology, GNITS, Hyderabad , Telangana, India.

*** Principal, Pydah College of Engineering and Technology, Visakhapatnam, Andhra Pradesh, India.

**** M.TechStudent, Department of Electrical and Electronics Engineering, Swarnandhra College of Engineering and Technology, Narasapuram, Andhra Pradesh, India.

Rao, V., Tulaisram, S.S., Brahmaiah, B., and Ramya. (2019). Features of PSO – BFOA Based Increment Conductance Method With FPGA. i-manager's Journal on Circuits and Systems , 7(1), 14-23. https://doi.org/10.26634/jcir.7.1.15391

Abstract

The global primary energy demands are increasing rapidly, which arrives at almost double the growth rate of energy consumption (Senjyu, Nakaji, Uezato, & Funabashi, 2005). An enhanced network-based control structure is essential, especially to get rid of the frequency deviations, power sharing errors, and stability concerns associated with the conservative droop control mainly in the micro grids (Jiang, Cao, Li, & Peng, 2012). One of the solutions for the issues is, to introduce renewable energy, among others PV and wind energy are clean and abundantly available in nature (Faranda & Leva, 2008). The Photovoltaic (PV) systems output power fluctuates according to the irradiation and temperature (weather conditions) (Kahrobaeian & Mohamed, 2015). Irregular PV output power results in frequency variations in the power systems, especially when the penetration is high. A photovoltaic (PV) array has nonlinear I-V (current-voltage) characteristics and its output power varies with solar insolation level, besides the ambient temperature. Only one point, called Maximum Power Point (MPP), exists on the P–V (power–voltage) curve, in which the power is maximum and the MPP fluctuates if there are changes in atmospheric conditions. The maximization of power output that takes place with greater efficiency becomes significant (Rao, Tulasiram, & Brahmaiah,2005). MPPT is the technique in use for extracting maximum power which is made available from the PV module (Subudhi & Pradhan, 2013). In this paper, a new hybrid algorithm is proposed combining the features of BFOA and Particle Swarm Optimization (PSO) for tuning PID controller, to give the better output from the solar power. PSO-BFOA based Incremental Conductance method to reduce sustained oscillations and fast searching of MPPT Computer simulations illustrate the effectiveness of the proposed approach compared to that of basic versions of PSO and BFO with FPGA. The results show that there are very good correlations between the controller parameters and the process parameters.

Optimal Allocation and Sizing of PV Distributed Generations under Several Loading Conditions

Volume 7 Issue 1 December - February 2019

Research Paper

Optimal Allocation and Sizing of PV Distributed Generations under Several Loading Conditions

Mahmoud A. Attia* , Mohamed Ezzat**, Ibrahim M. Diaaeldin***

*_** Assistant Professor, Department of Electric Power and Machines, Faculty of Engineering, Ain Shams University, Cairo, Egypt.

*** Research Scholar, Department of Engineering Physics and Mathematics, Faculty of Engineering, Ain Shams University, Cairo, Egypt.

Attia, M. A, Ezzat, M., and Diaaeldin, I. M (2019). Optimal Allocation and Sizing of PV Distributed Generations under Several Loading Conditions. i-manager's Journal on Circuits and Systems , 7(1), 1- 13. https://doi.org/10.26634/jcir.7.1.15250

Abstract

This paper aims to reduce the power losses and improve system reliabilty through finding optimal number, location, and sizing of Photovoltaic Distributed Generations (PV-DG). The PV-DG is modeled as a negative load, draws reactive power from grid and injects real power to the grid. Optimum allocation of PV-DGs and their sizing is obtained by Harmony Search Algorithm (HS) and Teaching-Learning-Based Optimization (TLBO) approaches. IEEE 33-bus distribution system was successfully demonstrated by that approach. HS has proven its superiority against TLBO algorithm as it uses less DGs rating devices to enhance distribution system performance. The new contribution in this research is to optimize the number of DGs that does not operate with a given number of DGs (1 DG , 2 DG ,…..) as most of the previous works. Another contribution is to study the optimization under several loading conditions.

Design and Verification of 16-Bit RISC Processor using SystemVerilog

Volume 6 Issue 4 September - November 2018

Research Paper

Design and Verification of 16-Bit RISC Processor using SystemVerilog

S. M. Bhagat* , S. U. Bhandari**

* PG Scholar, Department of Electronic and Telecommunication from Pimpri Chinchwad College of Engineering, Pune, Maharashtra, India.

** Professor, Department of Electronic and Telecommunication from Pimpri Chinchwad College of Engineering, Pune, Maharashtra, India.

Bhagat, S. M., Bhandari, S. U. (2018). Design and Verification of 16-Bit RISC Processor using System Verilog, i-manager's Journal on Circuits and Systems, 6(4), 38-41. https://doi.org/10.26634/jcir.6.4.14864

Abstract

The regularly increasing complexity and size of the designs faces various issues with traditional verification methods. To address this issue a reuse-oriented, verification methodology should be adopted which is built on the rich semantic support of a standard language. This paper presents a design of a 16 bit RISC processor with 15 instructions. The design is described in each module and the performance of the design is also presented in convenient manner. Although the design cycle takes time, but more time is required for verification. To perform verification process, verification environment is built for few modules of this RISC processor using SystemVerilog. Among various verification methodologies here a simple approach of verification is presented.