Domestic Wastewater Reclamation and Reuse in Nigeria: A Case Study of Some Selected Treatment Plants in Abuja and Lagos

Volume 15 Issue 1 August - October 2019

Research Paper

Domestic Wastewater Reclamation and Reuse in Nigeria: A Case Study of Some Selected Treatment Plants in Abuja and Lagos

Olasehinde Samuel Oloruntoba* , Alabi Tobi Michael**

*-** Department of Building, Federal University of Technology, Akure.

Oloruntoba, O. S., & Michael, A. T. (2019). Domestic Wastewater Reclamation and Reuse in Nigeria: A case study of some selected treatment plants in Abuja and Lagos. i-manager’s Journal on Future Engineering and Technology , 15(1), 1-10.

Abstract

The challenges facing the supply of potable water and the environmental nuisance that wastewater discharge is provoking in Nigeria cannot be underestimated. While most of the previous studies focused on industrial wastewater treatment, this study identified the challenges of domestic wastewater reclamation and reuse in Nigeria; assessed the methods of reclaiming domestic wastewater and examined the effects of reclaiming and reusing domestic wastewater in Nigeria with a view to providing information that will enhance the sustainable reuse of wastewater in Nigeria. The study used primary and secondary data. Primary data was collected from seven selected wastewater treatment plants in different geopolitical zones and Abuja municipal. It was sourced using site visits and google forms. Data collected include the challenges of reclaiming domestic wastewater, the method of reclamation, level of treatment operating and current ways of reusing domestic wastewater in their organization/estate, knowledge of domestic wastewater reclamation and reuse, ways in which reclaimed domestic wastewater can be reuse in Nigeria and effects of reclaiming and reusing domestic wastewater in Nigeria. The data were analyzed using frequency, percentages, content analysis and mean score (MS). Finding reveals that the major challenges of wastewater reclamation and reuse in Nigeria are; cost (it is capital intensive), erratic power supply, shortage of skilled personnel, sewage collection problem and ineffective public sewer while the methods of reclamation in use are activated sludge (extended aeration), anaerobic digestion, oxidation ponds and membrane filtration respectively. Furthermore majority of the wastewater treatment plant employed the tertiary level of treatment. The result of mean score showed that the effects of reclaiming and reusing domestic wastewater in Nigeria were to prevent breakout of waterborne diseases (MS=4.93), to prevent environmental pollution (MS=4.88) and rapid urban population growth (MS=4.85). The study also revealed that agricultural purposes should be the major way of reusing wastewater in Nigeria based on the analyzed data .The study concluded that breakout of waterborne diseases and environmental pollution are the major reasons why Nigeria should reclaim and reuse her domestic wastewater.

A Comparative Analysis Report on Modified Reversible Sequential Circuits realized with Improved Quantum cost

Volume 7 Issue 1 December - February 2019

Research Paper

A Comparative Analysis Report on Modified Reversible Sequential Circuits realized with Improved Quantum cost

Gopi Chand Naguboina* , T. Sravya**

* Assistant Professor, Department of Electronics and Communication Engineering, MaharajVijayaramGajapathi Raj (MVGR) College of Engineering (Autonomous), Vizianagaram, Andhra Pradesh, India.

** PG Scholar, Department of Electrical and Electronics Engineering, Sri PadmavatiMahilaVisvavidyalayam, Tirupati, Andhra Pradesh, India.

Naguboina, G. C., and Sravya, T. (2019). Transient Dynamic Finite Element Analysis of Cup Drawing Process. i-manager's Journal on Circuits and Systems , 7(1), 37-50. https://doi.org/10.26634/jcir.7.1.15243

Abstract

Reversible Logic is the dominating field of research in low power VLSI. In recent times, reversible logic has gained special attention in order to reduce power consumption mainly in concern to digital logic design. The main aim of this paper is to give an overall summary report on Digital sequential circuits like Shift registers and Counters designed using reversible logical computation. Digital circuits are the circuits implemented using Boolean logical expressions. Digital circuits find many applications in present daily life. Different types of combinational and sequential circuits are designed using reversible logic to reduce power dissipation. A Boolean function f(i1, i2, i3,……, in) having 'n' inputs and 'm' outputs is said to be logically reversible if the number of inputs are equal to the number of outputs (i.e. n = m) and the input pattern maps uniquely to the output pattern. Few reversible logic gates present in the literature are NOT gate, Feynman Gate (CNOT gate), Double Feynman Gate, Peres Gate, TR gate, Seynman Gate, etc. The reversible gate must run both forward and backward directions such that the inputs can be retrieved with the knowledge of outputs. Reversible Logic has applications in various fields like Quantum Computing, Optical Computing, Nano-technology, Computer Graphics, low power VLSI, etc. Reversible logic has gained essence in recent years largely due to its property of low power consumption and low heat dissipation. Till date in the literature, universal shift register and shift counters are realized using reversible logical computation for the first time in this paper. In this paper, a summary report is given on Sequential circuits like Shift registers and Counters designed using reversible logical computation with improved quantum cost. A comparative study on reversible and irreversible sequential logical circuits is also given. The realized reversible logical circuits are analysed in terms of quantum cost, garbage outputs, number of gates, and propagation delay. The circuits have been designed and simulated using Xilinx software.

Simulation of High Frequency Step Down of Single Phase Matrix Converter as an Universal Converter

Volume 7 Issue 1 December - February 2019

Research Paper

Simulation of High Frequency Step Down of Single Phase Matrix Converter as an Universal Converter

K. V. Divya Sree* , S. K. Ruksana**

* Assistant professor, Department of Electronics and Communication Engineering, Vasavi college of engineering, Hyderabad , Telangana,India.

** PG Scholar, Department of Electronics and Communication Engineering, Vasavi college of engineering, Hyderabad , Telangana,India.

Sree, D. K. V., and Ruksana, S. K. (2019). Transient Dynamic Finite Element Analysis of Cup Drawing Process. i-manager's Journal on Circuits and Systems , 7(1), 30-36. https://doi.org/10.26634/jcir.7.1.15726

Abstract

This paper presents the concept of single phase matrix converter as an universal converter for high frequency step down operation. Matrix converter implemented as an rectifier, chopper, inverter, and cyclo-converter for a high frequency step down has been presented in this paper. This will reduce the need for the new or an extra converter requirement. The technique used for the implementation of the proposed topology was sinusoidal pulse width modulation technique. This paper verifies the four possible conversion processes, such as AC-DC, DC-DC, DC-AC, and AC-AC from a high frequency input to the desired low frequency output by the single phase matrix converter alone. The results of the four conversion topologies along with the filter has been presented in this paper. The proposed topology has been implemented in the Matlab / Simulink software and the desired results for each of the converter topology has been verified.

High Speed and Low Power 4*4 Array Multiplier Design

Volume 7 Issue 1 December - February 2019

Research Paper

High Speed and Low Power 4*4 Array Multiplier Design

N. Suresh* , K. S. Shaji**, M. Chaitanya Kishore Reddy***

*_** Professor, Department of Electronics and Communication Engineering, Sphoorthy Engineering College, Hyderabad, Telangana, India.

*** Professor, Department of Computer Science Engineering, Sphoorthy Engineering College, Hyderabad, Telangana, India.

Suresh,N., Shaji, K. S., and Reddy, M. C. K. (2019). High Speed and Low Power 4*4 Array Multiplier Design. i-manager's Journal on Circuits and Systems , 7(1), 24-29. https://doi.org/10.26634/jcir.7.1.15530

Abstract

The main objective of this research is to design a Low power 4*4 Array Multiplier using modified GDI based full adder techniques, which consumes low power and have high speed computation compared to the CMOS technology. The modification has implemented in full adder design using GDI techniques in which the logical circuit reduces the number of transistors in the overall schematic. As we design any types of multiplier, the main logical block is adder and AND gate, similarly in this research also the authors concentrate to design Low power 4*4 Multiplier, which contains 8 full adder blocks. In these blocks, a modified GDI based full adder technology has been introduced. This way of reducing the number of transistors reduces the power consumption of overall circuits, propagation delay, and surface area. At the same time, the computation speed of the multipliers is increased.

Features of PSO – BFOA Based Increment Conductance Method with FPGA

Volume 7 Issue 1 December - February 2019

Research Paper

Features of PSO – BFOA Based Increment Conductance Method with FPGA

Ch. Venkateswara Rao* , S. S. Tulsiram**, B. Brahmaiah ***, Ch. Ramya****

* Lecturer, Department of Electrical and Electronics Engineering, Salalah College of Technology, Salalah, Oman.

** Dean and Professor, Department of Electrical and Electronics Engineering, Salalah College of Technology, GNITS, Hyderabad , Telangana, India.

*** Principal, Pydah College of Engineering and Technology, Visakhapatnam, Andhra Pradesh, India.

**** M.TechStudent, Department of Electrical and Electronics Engineering, Swarnandhra College of Engineering and Technology, Narasapuram, Andhra Pradesh, India.

Rao, V., Tulaisram, S.S., Brahmaiah, B., and Ramya. (2019). Features of PSO – BFOA Based Increment Conductance Method With FPGA. i-manager's Journal on Circuits and Systems , 7(1), 14-23. https://doi.org/10.26634/jcir.7.1.15391

Abstract

The global primary energy demands are increasing rapidly, which arrives at almost double the growth rate of energy consumption (Senjyu, Nakaji, Uezato, & Funabashi, 2005). An enhanced network-based control structure is essential, especially to get rid of the frequency deviations, power sharing errors, and stability concerns associated with the conservative droop control mainly in the micro grids (Jiang, Cao, Li, & Peng, 2012). One of the solutions for the issues is, to introduce renewable energy, among others PV and wind energy are clean and abundantly available in nature (Faranda & Leva, 2008). The Photovoltaic (PV) systems output power fluctuates according to the irradiation and temperature (weather conditions) (Kahrobaeian & Mohamed, 2015). Irregular PV output power results in frequency variations in the power systems, especially when the penetration is high. A photovoltaic (PV) array has nonlinear I-V (current-voltage) characteristics and its output power varies with solar insolation level, besides the ambient temperature. Only one point, called Maximum Power Point (MPP), exists on the P–V (power–voltage) curve, in which the power is maximum and the MPP fluctuates if there are changes in atmospheric conditions. The maximization of power output that takes place with greater efficiency becomes significant (Rao, Tulasiram, & Brahmaiah,2005). MPPT is the technique in use for extracting maximum power which is made available from the PV module (Subudhi & Pradhan, 2013). In this paper, a new hybrid algorithm is proposed combining the features of BFOA and Particle Swarm Optimization (PSO) for tuning PID controller, to give the better output from the solar power. PSO-BFOA based Incremental Conductance method to reduce sustained oscillations and fast searching of MPPT Computer simulations illustrate the effectiveness of the proposed approach compared to that of basic versions of PSO and BFO with FPGA. The results show that there are very good correlations between the controller parameters and the process parameters.

Optimal Allocation and Sizing of PV Distributed Generations under Several Loading Conditions

Volume 7 Issue 1 December - February 2019

Research Paper

Optimal Allocation and Sizing of PV Distributed Generations under Several Loading Conditions

Mahmoud A. Attia* , Mohamed Ezzat**, Ibrahim M. Diaaeldin***

*_** Assistant Professor, Department of Electric Power and Machines, Faculty of Engineering, Ain Shams University, Cairo, Egypt.

*** Research Scholar, Department of Engineering Physics and Mathematics, Faculty of Engineering, Ain Shams University, Cairo, Egypt.

Attia, M. A, Ezzat, M., and Diaaeldin, I. M (2019). Optimal Allocation and Sizing of PV Distributed Generations under Several Loading Conditions. i-manager's Journal on Circuits and Systems , 7(1), 1- 13. https://doi.org/10.26634/jcir.7.1.15250

Abstract

This paper aims to reduce the power losses and improve system reliabilty through finding optimal number, location, and sizing of Photovoltaic Distributed Generations (PV-DG). The PV-DG is modeled as a negative load, draws reactive power from grid and injects real power to the grid. Optimum allocation of PV-DGs and their sizing is obtained by Harmony Search Algorithm (HS) and Teaching-Learning-Based Optimization (TLBO) approaches. IEEE 33-bus distribution system was successfully demonstrated by that approach. HS has proven its superiority against TLBO algorithm as it uses less DGs rating devices to enhance distribution system performance. The new contribution in this research is to optimize the number of DGs that does not operate with a given number of DGs (1 DG , 2 DG ,…..) as most of the previous works. Another contribution is to study the optimization under several loading conditions.

Design and Verification of 16-Bit RISC Processor using SystemVerilog

Volume 6 Issue 4 September - November 2018

Research Paper

Design and Verification of 16-Bit RISC Processor using SystemVerilog

S. M. Bhagat* , S. U. Bhandari**

* PG Scholar, Department of Electronic and Telecommunication from Pimpri Chinchwad College of Engineering, Pune, Maharashtra, India.

** Professor, Department of Electronic and Telecommunication from Pimpri Chinchwad College of Engineering, Pune, Maharashtra, India.

Bhagat, S. M., Bhandari, S. U. (2018). Design and Verification of 16-Bit RISC Processor using System Verilog, i-manager's Journal on Circuits and Systems, 6(4), 38-41. https://doi.org/10.26634/jcir.6.4.14864

Abstract

The regularly increasing complexity and size of the designs faces various issues with traditional verification methods. To address this issue a reuse-oriented, verification methodology should be adopted which is built on the rich semantic support of a standard language. This paper presents a design of a 16 bit RISC processor with 15 instructions. The design is described in each module and the performance of the design is also presented in convenient manner. Although the design cycle takes time, but more time is required for verification. To perform verification process, verification environment is built for few modules of this RISC processor using SystemVerilog. Among various verification methodologies here a simple approach of verification is presented.

Detection of Rotor Broken Bar of an Induction Motor using S-Transform

Volume 6 Issue 4 September - November 2018

Research Paper

Detection of Rotor Broken Bar of an Induction Motor using S-Transform

Sudhir Agrawal* , V. K. Giri **, A. N. Tiwari***

* PhD Scholar, Department of Electrical Engineering, Madan Mohan Malaviya University of Technology, Gorakhpur, Uttar Pradesh, India.

** Director, Rajkiya Engineering College, Sonbhadra, Uttar Pradesh, India.

*** Professor, Department of Electrical Engineering, Madan Mohan Malaviya University of Technology, Gorakhpur, Uttar Pradesh, India.

Agrawal, S., Giri, V. K., Tiwari, A. N. (2018). Detection of Rotor Broken Bar of an Induction Motor using S-Transform, i-manager's Journal on Circuits and Systems, 6(4), 31-37. https://doi.org/10.26634/jcir.6.4.15113

Abstract

Induction motors are the one of the most important production machines of any industry around the world. Therefore, the condition monitoring of induction motors is very important for successful and profitable running of an industry. Broken rotor bars are one of the critical health problems of any induction motor. To tackle this, application of Stockwell- Transform (ST) is presented in this paper. ST has been applied on the simulated signal of rotor broken bar and the results are compared with the Fast Fourier Transform method, which is a frequency domain analysis method. Normally, frequency domain analysis fails to detect the broken bar of the rotor if the severity of damage is low. The results obtained by applying ST confirms that the ST transform is able to detect the breakage of rotor bar better if the damage level is small.

Design of Area Efficient Encoder and Decoder using Quantum DOT Cellular Automata

Volume 6 Issue 4 September - November 2018

Research Paper

Design of Area Efficient Encoder and Decoder using Quantum DOT Cellular Automata

Mrunalini M. Kamble* , Deepti S. Khurge**

* P.G. Student, Department of Electronic & Telecommunication, Pimpri Chinchwad College of Engineering, Pune, Maharashtra, India.

** Assistant Professor, Department of Electronic & Telecommunication, Pimpri Chinchwad College of Engineering, Pune, Maharashtra, India.

Kamble, M., Khurge,D. S. (2018). Design of Area Efficient Encoder and Decoder using Quantum Dot Cellular Automata, i-manager's Journal on Circuits and Systems, 6(4), 26-30. https://doi.org/10.26634/jcir.6.4.14942

Abstract

As an alternative to CMOS-VLSI, researchers have proposed new technologies like FINFET, CNTFET, MTJ to reduce the scalability of the device. A new computing paradigm with quantum dots called Quantum dot Cellular Automata (QCA) is a polarization based digital logic architecture. QCA cell is the basic unit to build logic gates and devices in quantum domain. It proposes an effective design of logic gates and arithmetic circuit using QCA. Here the half and full adder is designed using minimum number of QCA cells with no crossover and compared with previous results. So these designs can be used to construct complex circuits. The simulations of the present work have been carried out by means of QCA designer tools. The simulation results help to implement large digital circuits in nanoscalerange.

Early, Demagnetization Assessment of PMSM Machine by Discrete Wavelet Transform

Volume 6 Issue 4 September - November 2018

Research Paper

Early, Demagnetization Assessment of PMSM Machine by Discrete Wavelet Transform

Khadim Moin Siddiqui* , S. Chatterji**

* Associate Professor and Head, Department of Electrical Engineering, Guru Nanak Institute of Engineering & Management, Hoshiarpur, Punjab, India.

** Group Director, Shri Guru Nanak Dev Education Trust, Dalewal, Hoshiarpur, Punjab, India.

Siddiqui, K. M., Chatterji, S. (2018). Early, Demagnetization Assessment of PMSM Machine by Discrete Wavelet Transform, i-manager's Journal on Circuits and Systems, 6(4), 16-25. https://doi.org/10.26634/jcir.6.4.15214

Abstract

Nowadays, in many applications, the Permanent Magnet Synchronous Motor (PMSM) has become an alternative to induction machines due to its reliability and excellent dynamic performance. Therefore, the PMSM are being used in the large variety of applications, especially in automotive or high power traction systems. In this motor, the diagnosis of magnetic status has become a challenging task for many researchers since a decade. Therefore, in this research paper an attempt has been made to solve the above problem and trying to diagnose magnetic demagnetization in the early stage precisely. The magnetic demagnetization of the PMSM has been diagnosed with the help of a proposed simulation model. In the simulation model, various stages of magnetic demagnetizations have been created by varying some physical parameters and have been diagnosed in the early stages by applying advanced wavelet transform technique. For diagnosis of magnetic demagnetization, two approaches have been used; first is the time domain technique and second is the time-frequency domain technique.

Trioengineering: The Procedures that Use Trioinformatics Neuroengineering Neuromathematics Notation to Express, Build, Define, and Inform the Application of the Trichotomous–Based Inquiry in Digital Research Design

Volume 6 Issue 4 September - November 2018

Research Paper

Trioengineering: The Procedures that Use Trioinformatics Neuroengineering Neuromathematics Notation to Express, Build, Define, and Inform the Application of the Trichotomous–Based Inquiry in Digital Research Design

James Edward Osler II*

Professor, School of Education, North Carolina Central University, USA.

Osler II, J. E. (2018). Trioengineering: The Procedures that Use Trio informatics Neuro engineering Neuromathematics Notation to Express, Build, Define, and Inform the Application of the Trichotomous–Based Inquiry in Digital Research Design, i-manager's Journal on Circuits and Systems, 6(4), 1-15. https://doi.org/10.26634/jcir.6.4.15093

Abstract

This discourse provides a deeper epistemological rational for the novel discipline of “Trioinformatics” through the use of “Trioengineering”. Trioengineering uses of the novel mathematical “Ambitation” or “Neuromathematical Neuroengineering Notation”. This specialized operation that is the Trioinformatics article appeared in the March–May imanager’s Journal on Circuits and Systems. Trioengineering use of the neuromathematics “Ambitation” is the holistic, collaborative, and comprehensive expression of Trioinformatics as a sequential sequence of inquiry into a precise research analysis methodology. Neuroengineering is an innovative way of explaining the transition from trichotomous logic (Osler, 2015) into trichotomous Triple–I (Osler, 2013d) research questions and associated instrumentation [first introduced in the i-manager’s Journal on Mathematics as a part of the Tri–Squared Test (Osler, 2012a)].Trioinformatics is an in–depth way of symbolically illustrating the law of trichotomy and a mathematically–grounded rational technique for explaining the ternary nature of electronic circuitry (Osler, 2015). The use of the Trioinformatics also adds value to investigative inquiry through the efficacy of digital instruments and tools via eduscientifically–engineered (Osler, 2013a) research designs (Osler, 2015).

Implementation of Reversible Logic Gate (Peres Gate) to Design a Half Adder for Low Power with Reduced Area and Improved Efficiency

Volume 6 Issue 3 June - August 2018

Research Paper

Implementation of Reversible Logic Gate (Peres Gate) to Design a Half Adder for Low Power with Reduced Area and Improved Efficiency

Tripti Nirmalkar* , Deepti Kanoujia**, Kshitiz Varma***

* PG Scholar, Department of Electronics and Communication Engineering, Chhattisgarh Swami Vivekananda Technical University,Chhattisgarh, India.

** Post Graduate, Department of Electronics and Communication Engineering, Sri Shankaracharya College of Engineering and Technology, Chhattisgarh, India.

*** Project Officer, Department of Electronics and Communication Engineering, Chhattisgarh Swami Vivekananda Technical University, Chhattisgarh, India.

Nirmalkar, T., Kanoujia, D., and Varma, K. (2018). Implementation of Reversible Logic Gate (Peres Gate) to Design a Half Adder for Low Power with Reduced Area and Improved Efficiency. i-manager’s Journal on Circuits and Systems, 6(3), 36-42. https://doi.org/10.26634/jcir.6.3.14877

Abstract

Research on reversible logic gates has become one of the interesting fields in the world of electronics. This has been proved to be one of the most reliable logics that originates its place in low power CMOS skills, Nano and optical calculation and many more. These broadsheet offers the comparison of different reversible logic gates in expressions of quantum cost, delay, transistor charge, and also implementation of one of the alterable logic gates, i.e. Peres gate in a conventional half adder with the help of an efficient algorithm. The work is performed in Xilinx using Verilog coding. The simulation result shows improved efficiency, low power, and low area consumption as related to the standard half adder. This half adder can be utilized in different applications, where circuit comprising of a conventional half adder can be replaced by Peres Half Adder (HAP).

Validation of IOV chain using OVM Technique

Volume 6 Issue 3 June - August 2018

Research Paper

Validation of IOV chain using OVM Technique

S. Gayathri* , S. Lavanya **

* Professor, Department of Electronics and Communication Engineering, Sri Jayachamarajendra College of Engineering, Mysuru, Karnataka, India.

** Department of Electronics and Communication Engineering, Sri Jayachamarajendra College of Engineering, Mysuru, Karnataka, India.

Gayathri, S., and Lavanya, S. (2018). Validation of IOV Chain using OVM Technique. i-manager’s Journal on Circuits and Systems, 6(3), 28-35. https://doi.org/10.26634/jcir.6.3.14632

Abstract

Today, the utilization of pre-silicon system verification strategies within the business cannot guarantee that every error in system computer code or system hardware are discovered and removed before silicon (Si) becomes offered. Some system errors solely show up once the application software package is executed on the particular Si. Presently, the business spends on average more than 50% of the overall project time on post-silicon validation and debugging. At this stage, it is still terribly tough and time intense to rectify issues that ends up in higher development price, slippery deadlines, and a possible loss of consumer. Therefore, an efficient method for debugging errors is used called Design for Debug (DFD). The DFD strategies prevailing nowadays are everywhere for over a decade. There are numerous examples throughout the industry, where the inclusion and subsequent use of DFD features have contributed significantly to a reduction in Time to Market (TTM). This paper proposes a DFD Validation of In-die variation (IDV), On-die Droop inducer (ODI), and Voltage Droop monitor (VDM) to reduce manufacturing defects or errors of chip, such as Variation of Process, Power Domain voltages and also variation of current inducer needed for chip.

Double Node Upset Radiation Immune Latch Design in 65 nm CMOS Technology

Volume 6 Issue 3 June - August 2018

Research Paper

Double Node Upset Radiation Immune Latch Design in 65 nm CMOS Technology

Sandhya Kesharwani* , Vaibhav Dedhe**

* PG Scholar, Department of Electronics and Telecommunication, Shri Shankaracharya Technical Campus, Chhattisgarh, India.

** Assistant Professor, Department of Electronics and Telecommunication, Shri Shankaracharya Technical Campus, Chhattisgarh, India.

Kesharwani, S., and Dedhe, V. (2018). Double Node Upset Radiation Immune Latch Design in 65nm CMOS Technology. i-manager’s Journal on Circuits and Systems, 6(3), 21-27. https://doi.org/10.26634/jcir.6.3.14624

Abstract

The space environment is characterized with various energetic particles like cosmic rays, cosmic neutrons, alpha particles and heavy ions from solar flares. Nowadays most of the circuits used in space applications are being made of Complementary Metal Oxide Semiconductor (CMOS). The technology is scaling down, i.e. reduction in supply voltage and node capacitances lead to decrease of amount of charge stored on a node, which makes the circuit more vulnerable towards particle induced charge. When amount of this particle induced charge is high enough, a transient fault appears like a glitch called as Single Event Transient (SET). As the feature size scales down, the vulnerability of circuits to radiation induced error has also been increased, as this may cause Double Node Upset (DNU) i.e Single Event Double Node Upset (SEDU). In this paper, some of the best known designs to mitigate the Single Event Upset as well as Single Event Double Node Upset in 65 nm CMOS technology using standard TSPICE tool has been discussed. The comparison of those designs on the same platform i.e 65 nm technology is presented, their power consumption and propagation delay are also compared.

Design of Router for 2 users and 4 users using Reversible Logic in Quantum Cellular Automata

Volume 6 Issue 3 June - August 2018

Research Paper

Design of Router for 2 users and 4 users using Reversible Logic in Quantum Cellular Automata

R. Gurunadha*

* Assistant professor, Department of Electronics and Communication Engineering, JNTUK-University College of Engineering Vizianagaram, Andhra Pradesh, India.

R.Gurunadha, (2018). Design of Router for 2 users and 4 users using Reversible Logic in Quantum Cellular Automata. i-manager’s Journal on Circuits and Systems, 6(3), 15-20. https://doi.org/10.26634/jcir.6.3.14876

Abstract

The complexity of circuit designing has been increasing by immense increase of applications in this field. One of the major complexities is power dissipation. Reversible Logic Design can be used to reduce this complexity, which is gaining demand day by day and having applications in low power CMOS circuits, optical computing, quantum computing, and nanotechnology. Power dissipation of VLSI chips becomes a crucial aspect as complexity of applications grow very rapidly. High power dissipation in electronic devices decreases battery lifetime. A router is a key component for transmitting data between two users. It is a networking device, commonly specialized for forwarding data packets between computer networks. In this paper, the author has designed a router using reversible logic in QCA designer. An advantage of quantum phenomena is taken by QCA and, it may ultimately slow down the progress in scaling down CMOS circuits.

Novel Setup Time Model for Standard Cell Library Characterization

Volume 6 Issue 3 June - August 2018

Research Paper

Novel Setup Time Model for Standard Cell Library Characterization

Pravee Jain* , Sharad Mohan Shrivastava**

* PG Scholar, Department of Electronics and Communication Engineering, Sagar Institute of Science and Technology, Bhopal, Madhya Pradesh, India.

** Assistant Professor, Department of Electronics and Communication, Sagar Institute of Science and Technology, Bhopal, Madhya Pradesh, India.

Jain, P., and Shrivastava, S., M. (2018). Novel Setup Time Model for Standard Cell Library Characterization. i-manager’s Journal on Circuits and Systems, 6(3), 9-14. https://doi.org/10.26634/jcir.6.3.14566

Abstract

In digital VLSI design calculation of setup/hold time is very important part. Setup/hold time defines the maximum speed of the circuit on which it can work. When a design is completed the first step is to check the timing performances of circuit using Static Timing Analysis (STA) (Scheffer et al., 2006). Accuracy of STA depends on the data described in standard cell libraries. So accuracy of STA depends on accuracy of standard cell library characterization (Cirit, 1991; Roethig, 2003; Patel, 1990; Phelps, 1991). As the technology is scaling down, the characterization of standard cell libraries are becoming more time consuming and requires large computational time. Further due to process, voltage and temperature (PVT) variations standard cell library characterization is done for various PVT, this increase characterization greatly. In this paper we present a novel approach to speed up standard cell library characterization for true single phase clocked (TSPC) latch (Yuan and Svensson, 1989) setup time by developing a linear setup time model. In this model setup time varies linearly with output load capacitance (CL) and input transition time (TR). We express setup time model coefficients as a function of logic gate size (Wn) of the latch. We do not use device current/capacitance models in derivation of model, so it is valid with technology scaling. Using proposed model approximately 70% SPICE simulation during the standard cell library characterization for latch setup time can be saved. We observed that setup time calculated using proposed model is within 2% (average) of that calculated using simulation.

Trends in ESD Protection Design for I/O Libraries in Advanced CMOS and FINFET Technologies

Volume 6 Issue 3 June - August 2018

Research Paper

Trends in ESD Protection Design for I/O Libraries in Advanced CMOS and FINFET Technologies

Oleg Semenov * , Lyubov Leskova**, Svetlana Gerasimova ***, Dmitry Vasiounin****

* Project Leader, NXP Semiconductors, Moscow, Russia.

**,*** Layout designer, NXP Semiconductors, Moscow, Russia.

**** Circuit Design Engineer, NXP Semiconductors, Moscow, Russia.

Semenov, O., Leskova, L., Gerasimova, S., and Vasiounin, D. (2018). Trends in ESD Protection Design For I/O Libraries in Advanced CMOS and Finfet Technologies. i-manager’s Journal on Circuits and Systems, 6(3), 1-8. https://doi.org/10.26634/jcir.6.3.14878

Abstract

This paper discusses the trends in ESD protection design used in I/O libraries in advanced CMOS and FinFet technologies. The trends and guidelines are provided predominantly for low voltage I/O libraries that are commonly used for general purpose interfaces and industrial low voltage interfaces such as, GPIO, DDR, LVDS, etc. Additionally, the impact of technology scaling on ESD qualification targets for CDM stress is considered.

Radiation Immune Latch design in CMOS Technology:A Review

Volume 6 Issue 2 March - May 2018

Review Paper

Radiation Immune Latch design in CMOS Technology:A Review

Sandhya Kesharwani* , Vaibhav Dedhe**

* PG Scholar, Department of Electronics and Telecommunication Engineering, Shri Shankaracharya Technical Campus, Chhattisgarh, India.

** Assistant Professor, Department of Electronics and Telecommunication Engineering, Shri Shankaracharya Technical Campus, Chhattisgarh, India

Kesharwani, S., and Dedhe, V. (2018). Radiation Immune Latch Design In CMOS Technology: A Review. i-manager’s Journal on Circuits and Systems, 6(2), 39-46. https://doi.org/10.26634/jcir.6.2.14290

Abstract

The Space environment is characterized with various energetic particles like cosmic rays, cosmic neutrons, alpha particles,heavy ions from solar flares. Nowadays most of circuit used in space applications being made using CMOS. As the technology scaling down i.e reduction in supply voltage and node capacitances leads in decrease of amount of charge stored on a node,which makes the circuit more vulnerable towards particle induced charge, when amount of this particle induced charge is high enough,a transient fault gets appear like a glitch called as Single Event Transient(SET). As the feature size scales down, the vulnerability of circuits to radiation induced error has also been increased, as this may cause Double node upset i.e Single Event Double NodeUpset(SEDU).Here we would design and discuss some of the best known designs to mitigate the Single Event Upset as well as SingleEvent Double Node Upset in 65nm CMOS technology using standard TSPICE tool.We are comparing those designs on the same platform i.e 65nm technology and compare their power consumption and propagation delay.

A Review on Approximation Techniques for Arithmetic Adders

Volume 6 Issue 2 March - May 2018

Review Paper

A Review on Approximation Techniques for Arithmetic Adders

S. M. Bhagat*

Department of Electronics and Telecommunication Engineering, Pimpri Chinchwad College of Engineering, Pune, India.

Bhagat, S. M. (2018). A Review on Approximation Techniques for Arithmetic Adders. i-manager’s Journal on Circuits and Systems, 6(2), 33-38. https://doi.org/10.26634/jcir.6.2.14313

Abstract

To design the computing system, energy efficiency is an important issue to be considered. Approximate computing has been evolved as an optimistic solution for energy efficient design of digital systems. While designing these systems, power dissipation is the significant issue for integrated circuits in nanometric Complementary Metal Oxide Semiconductor (CMOS) technology. Approximate implementations of a circuit have been considered as a potential solution for applications in which exact result is not required, which eventually reduces power consumption. The approximate computing has various research activities which varies from programming languages to transistor levels. Here, different approximate adder circuits have been reviewed, which are based on XOR and XNOR gates, and majority gates. Where emerging nanotechnology exploit these majority gates, combining with approximate computing gives the potential to reduce power consumption. Approximate circuit provides low power consumption, low transistor count, less area and reduced delay. Hence it is a good option, when strict exact solution is not required. This paper is about the survey on arithmetic circuits and different design topologies such as Quantum Dot Cellular Automata (QCA)and Nanomagnetic Logic (NML)

Realization and Synthesis of Shift Registers and Shift Counters using Reversible Logical Computation

Volume 6 Issue 2 March - May 2018

Research Paper

Realization and Synthesis of Shift Registers and Shift Counters using Reversible Logical Computation

Gopi Chand Naguboina* , K. Anusudha**

* Department of Electronics and Communication Engineering, MVGR College of Engineering (A), Vizianagaram, Andhra Pradesh, India.

** Department of Electronics Engineering, Pondicherry University, Pondicherry, India.

Naguboina, G.C., and Anusudha, K. (2018). Realization and Synthesis of Shift Registers and Shift Counters using Reversible Logical Computation. i-manager’s Journal on Circuits and Systems, 6(2), 22-32. https://doi.org/10.26634/jcir.6.2.14759

Abstract

Reversible Logic is the dominating field of research in low power Very-Large-Scale Integration (VLSI). In recent time, reversible logic has gained special attention in order to reduce power consumption mainly in concern to digital logic design. The main aim of this paper is to realize and synthesize shift counters like Ring counter and Johnson ring counter using reversible logic. Shift Counter is a sequential circuit that performs counting through shifting operation in a loop fashion. The output of last register of the circuit will be fed to the input of first register. Ring counter owns its applications in clock division circuits, square wave generators, hardware logic design of Application-Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA) circuits etc., Ring counter and Johnson Ring counter are designed using reversible logic to reduce power dissipation. A Boolean function f (i1 , i2 , i3 , ……, i n) having 'n' inputs and 'm' outputs is said to be logically reversible, if the number of inputs are equal to the number of outputs ( i.e. n = m) and the input pattern maps uniquely to the output pattern. Few reversible logic gates present in the literature are NOT gate, Feynman Gate (CNOT gate), Double Feynman Gate, Peres Gate, TR gate, Seynman Gate etc. The reversible gate must run both in forward and backward directions such that the inputs can be retrieved with the knowledge of outputs. The two limitations of logical reversibility are Fan-out and Feed-back are not allowed. Signals from required output lines are duplicated to desired lines using additional reversible combinational circuits to overcome the Fan-out limitation. Reversible Logic has applications in various fields like Quantum Computing, Optical Computing, Nanotechnology, Computer Graphics, Low power VLSI etc. Reversible logic has gained essence in recent years largely due to its property of low power consumption and low heat dissipation. In this paper, shift registers like shift right register and shift left register which have less heat dissipation and low power consumption is proposed. Till date, shift counters are not yet designed using reversible logic. In this paper, an attempt has been made to design shift counters like ring counter and Johnson ring counter using reversible logic. The designed circuits are analysed in terms of Quantum Cost (QC), Garbage Outputs (GO) and number of gates. The circuit has been designed and simulated using Xilinx software.

Performance of Continuous and Discontinuous Space Vector Pwm Technique for Open End Winding Induction Motor Drive

Volume 6 Issue 2 March - May 2018

Research Paper

Performance of Continuous and Discontinuous Space Vector Pwm Technique for Open End Winding Induction Motor Drive

Syed Munvar Ali* , V. Vijaya kumar Reddy**, M. Surya Kalavathi***

* Research Scholar, JNTUH College of Engineering, Andhra Pradesh, India.

** Director, NBKR Institute of Science and Technology, Nellore, Andhra Pradesh, India.

*** Professor, Department of Electrical and Electronics Engineering, JNTUH College of Engineering, Andhra Pradesh, India.

Ali, S. M., Reddy, V. V. K., and Kalavathi, M. S. (2018). Performance of Continuous and Discontinuous Space Vector PWM Technique for Open End Winding Induction Motor Drive. i-manager’s Journal on Circuits and Systems, 6(2), 13-21. https://doi.org/10.26634/jcir.6.2.14558

Abstract

In this paper, a decoupled Space Vector Pulse Width Modulation (SVPWM) technique for indirect vector controlled induction motor drive in open end winding configuration is presented. The decoupled space vector PWM technique provides independent control of each inverter in an Open End Winding Induction Motor (OEWIM) drive. With this advantage, failure of any one inverter in the drive can be operated with reduced output voltage. With the freedom in selecting different voltage vectors for each inverter, this decoupled PWM technique also reduces the Common Mode Voltage (CMV), when compared with other coupled PWM techniques. Within a sample time T , in conventional s continuous decoupled space vector PWM technique, each inverter is operated with zero voltage vectors and active voltage vectors. In this paper to reduce the CMV with good quality of output voltage inverters with different continuous and discontinuous PWM (DPWM) techniques were presented. Within a sample time T , these PWM techniques use active s vectors, but zero voltage vectors may be replaced by new active vectors or zero vectors which are unequally shared. The performance of these PWM techniques were analyzed in MatLab/Simulink and the results were presented.

Comparison of Power and Latency Optimized 7t SRAM Bit-Cell With 6t SRAM Bit-Cell

Volume 6 Issue 2 March - May 2018

Research Paper

Comparison of Power and Latency Optimized 7t SRAM Bit-Cell With 6t SRAM Bit-Cell

G. Shivaprakash* , D. S. Suresh **

* Research Scholar and Associate Professor, Department of Electronics and Instrumentation Engineering, Ramaiah Institute of Technology, Bengaluru, Karnataka, India.

** Professor, Department of Electronics and Communication Engineering, Chennabasaveshwara Institute of Technology, Tumkure, Karnataka, India.

Shivaprakash, G., and Suresh, D. S. (2018). Comparison of Power and Latency Optimized 7t SRAM Bit-Cell With 6t SRAM Bit-Cell. i-manager’s Journal on Circuits and Systems, 6(2), 8-12. https://doi.org/10.26634/jcir.6.2.14760

Abstract

In today's smart digital world, for any digital circuit, one of the most vital parts is Static Random Access Memory (SRAM). The power consumption, speed, area etc. have been the major areas of concern in the evolution of different memory architectures. Researchers are working on the modification of basic 6T SRAM cell to meet their requirements by optimizing the performance parameters of SRAM. In the present research work, a novel 7T SRAM cell has been designed, having both low latency and low power. The proposed design has allowed control over threshold voltage and reduced the leakage current. As a consequence, there is a reduction in the static power consumption and load capacitance of SRAM. Dynamic power consumption, Static power consumption, Unit cell delay, Power Delay Product (PDP), Static Noise Margin (SNM) and Write SNM are estimated for 6T and 7T for comparison. On comparison of the performance parameters, the proposed 7T SRAM cell was found to be the cell with least power consumption along with lowest latency among the two cells. Most of the compared parameters show an improvement in the performance of the proposed design as compared to the regular 6T configuration of SRAM. This research was carried out using Cadence Virtuoso Tools on 90 nm technology with Assura Verification tool and Spectre simulation tool.

Leakage Power Reduction Using Multi Modal Driven Hierarchical Power Mode Switches

Volume 6 Issue 2 March - May 2018

Research Paper

Leakage Power Reduction Using Multi Modal Driven Hierarchical Power Mode Switches

Chandra Sekhar Reddy* , P. Ramana Reddy **

*Research Scholar, Department of Electronics and Communication Engineering, JNTUACEA, Anantapuramu, Andhra Pradesh, India.

** Professor, Department of Electronics and Communication Engineering, JNTUACEA, Anantapuramu, Andhra Pradesh, India..

Reddy, M. C. S., and Reddy, P. R. (2018). Leakage Power Reduction Using Multi Modal Driven Hierarchical Power Mode Switches. i-manager’s Journal on Circuits and Systems, 6(2), 1-7 https://doi.org/10.26634/jcir.6.2.14291

Abstract

This article presents a scalable power-gating scheme approach to reduce leakage power using intermediate poweroff modes. An important limitation in power-gating scheme is its variations with wakeup time during activation mode changes, as is often the case. The authors have proposed a novel power-gating scheme that are accomplished by hierarchical mode activation to reduce worst case delay bound. The system combines the advantages of leakage power reduction and wake up time optimization. The influence of power-gating scheme on circuit performance is studied and concluded that finite power-off modes, scalable modes are important for good performance. Key selection of power-off modes over entire circuit is complex and it is computationally more expensive. To get more accurate modes with finite trade off in wake up time, this new approach gives near-perfect ways of isolating modes from other changes. The complete power-gating scheme system was evaluated on a multiplier logic core as a test sample and also compared against well known power-gating schemes.

Performance Parameters of Low Power SRAM cells: A Review

Volume 6 Issue 1 December - February 2018

Research Paper

Performance Parameters of Low Power SRAM cells: A Review

Nidhi Tiwari* , Vaibhav Neema**, Kamal J Rangra***, Yogesh Chandra Sharma****

* Research Scholar, Department of Electronics and Communication Engineering, Vivekananda Global University, Jaipur, India.

** Assistant Professor, Department of Electronics and Communication Engineering, Institute of Engineering and Technology, Devi Ahilya University, Indore, India.

*** Chief Scientist, Transducers and Actuators Group, CSIR-CEERI, Pilani, India.

**** Professor, Department of Physics, Vivekananda Global University, Jaipur, India.

Tiwari, N., Neema, V., Rangra, K. J., and Sharma, Y. C. (2018). Performance Parameters of Low Power SRAM cells: A Review. i-manager’s Journal on Circuits and Systems, 6(1), 25-34. https://doi.org/10.26634/jcir.6.1.14495

Abstract

In this paper, various Low Power SRAM cell design techniques have been reviewed on the basis of power, stability, and delay. Many studies have proposed various SRAM architectures for different applications. It has been reported that 6T SRAM cell are high in speed but at low supply voltage, stability is a critical issue. It is found that 8T SRAM cell shows the highest level of stability at low supply voltage, but it has area penalty. Hence in this work all the required performance parameters of various SRAM cell architectures have been reviewed. This work will be helpful for VLSI designer to choose proper memory architecture as per applications. For example, machine learning needs high performance memory block while bio-medical implants require low power memory block. This paper also presents various tradeoffs between various design parameters of SRAM.