An Optimized Low Power Self-Resetting Logic Design Approach

Vol. 4  Issue 2
Year: 2016
Issue:Mar-May
Title:An Optimized Low Power Self-Resetting Logic Design Approach
Author Name:Shivani Kulshrestha and Vikas Kumar Rai
Synopsis:

This paper presents a new optimized technique to power reduction and performance improvement based on selfresetting logic. The concept of self-resetting logic uses the concept of resetting the output logic automatically after a certain time span. The proposed circuit eliminates the problems of SRLGDI logic proposed previously. SRLGDI was proven to be better than dynamic logic, CMOS self-resetting logic and GDI. Three designs of full adders were made using SRLGDI and a final proposed design was made using modified SRLGDI logic and compared to three SRLGDI designs to prove the performance improvement achieved using the modified SRLGDI logic.