An Efficient Hybrid PFSCL based Implementation of Asynchronous Pipeline

Vol. 4  Issue 3
Year: 2016
Issue:Jun-Aug
Title:An Efficient Hybrid PFSCL based Implementation of Asynchronous Pipeline
Author Name:Naman Saxena, Shruti Dutta and Neeta Pandey 
Synopsis:

In this paper, Positive Feedback Source Coupled Logic (PFSCL) based asynchronous pipeline implementation is addressed. Existing Conventional PFSCL and a more efficient Triple-Tail Cell-based PFSCL variant are used for this purpose. Striking a trade-off between both topologies, a new hybrid implementation of the pipeline has been proposed. The concept is elucidated through FIFO sequencer. The hybrid implementation of asynchronous pipeline results in lesser number of gates as well as lower average power dissipation, thus not only making the circuit more efficient but also reducing overall
area overhead. The validity of the proposal is confirmed through SPICE simulations using 0.18 um CMOS technology parameters.